We noticed that, per the XLR processor documentation, clz has a
different latency than other alu instructions. Also, the branch-likely
instructions are documented as obsolete on this target. This patch
makes some fairly obvious tweaks to address both issues.
This is another patch we've had in our local source base for some time.
OK for mainline?
-Sandra
2012-08-03 Catherine Moore <c...@codesourcery.com>
Sandra Loosemore <san...@codesourcery.com>
gcc/
* config/mips/xlr.md (ir_xlr_alu_clz): New insn_reservation.
(ir_xlr_alu): Remove clz.
* config/mips/mips-cpus.def (xlr): Set PTF_AVOID_BRANCHLIKELY.
Index: gcc/config/mips/xlr.md
===================================================================
--- gcc/config/mips/xlr.md (revision 190052)
+++ gcc/config/mips/xlr.md (working copy)
@@ -28,10 +28,15 @@
(eq_attr "type" "slt"))
"xlr_main_pipe")
+(define_insn_reservation "ir_xlr_alu_clz" 2
+ (and (eq_attr "cpu" "xlr")
+ (eq_attr "type" "clz"))
+ "xlr_main_pipe")
+
;; Integer arithmetic instructions.
(define_insn_reservation "ir_xlr_alu" 1
(and (eq_attr "cpu" "xlr")
- (eq_attr "type" "move,arith,shift,clz,logical,signext,const,unknown,multi,nop,trap,atomic,syncloop"))
+ (eq_attr "type" "move,arith,shift,logical,signext,const,unknown,multi,nop,trap,atomic,syncloop"))
"xlr_main_pipe")
;; Integer arithmetic instructions.
Index: gcc/config/mips/mips-cpus.def
===================================================================
--- gcc/config/mips/mips-cpus.def (revision 190053)
+++ gcc/config/mips/mips-cpus.def (working copy)
@@ -142,7 +142,7 @@ MIPS_CPU ("20kc", PROCESSOR_20KC, 64, PT
MIPS_CPU ("sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY)
MIPS_CPU ("sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY)
MIPS_CPU ("sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY)
-MIPS_CPU ("xlr", PROCESSOR_XLR, 64, 0)
+MIPS_CPU ("xlr", PROCESSOR_XLR, 64, PTF_AVOID_BRANCHLIKELY)
MIPS_CPU ("loongson3a", PROCESSOR_LOONGSON_3A, 64, PTF_AVOID_BRANCHLIKELY)
/* MIPS64 Release 2 processors. */
