Re: [PATCH] RISC-V: Recognized Svrsw60t59b extension

[Craig Blackmore]

On 20/03/2025 08:11, Mingzhu Yan wrote:
This patch support svrsw60t59b extension[1].
To enable GCC to recognize and process svrsw60t59b extension correctly at 
compile time.
[1] https://github.com/riscv/Svrsw60t59b

gcc/ChangeLog:

         * common/config/riscv/riscv-common.cc: New extension.
         * config/riscv/riscv-opts.h: New mask.

gcc/testsuite/ChangeLog:

         * gcc.target/riscv/arch-45.c: New test.

Signed-off-by: Mingzhu Yan <yanming...@iscas.ac.cn>
---
  gcc/common/config/riscv/riscv-common.cc  | 16 +++++++++-------
  gcc/config/riscv/riscv.opt               |  2 ++
  gcc/doc/invoke.texi                      |  8 ++++++++
  gcc/testsuite/gcc.target/riscv/arch-45.c |  5 +++++
  4 files changed, 24 insertions(+), 7 deletions(-)
  create mode 100644 gcc/testsuite/gcc.target/riscv/arch-45.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 5038f0eb959..418bd10a132 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -409,10 +409,11 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
    {"ssstateen", ISA_SPEC_CLASS_NONE, 1, 0},
    {"sstc",      ISA_SPEC_CLASS_NONE, 1, 0},
  
-  {"svinval", ISA_SPEC_CLASS_NONE, 1, 0},
-  {"svnapot", ISA_SPEC_CLASS_NONE, 1, 0},
-  {"svpbmt",  ISA_SPEC_CLASS_NONE, 1, 0},
-  {"svvptc",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"svinval",     ISA_SPEC_CLASS_NONE, 1, 0},
+  {"svnapot",     ISA_SPEC_CLASS_NONE, 1, 0},
+  {"svpbmt",      ISA_SPEC_CLASS_NONE, 1, 0},
+  {"svvptc",      ISA_SPEC_CLASS_NONE, 1, 0},
+  {"svrsw60t59b", ISA_SPEC_CLASS_NONE, 1, 0},
  
    {"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
    {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1732,9 +1733,10 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
    RISCV_EXT_FLAG_ENTRY ("zcmp", x_riscv_zc_subext, MASK_ZCMP),
    RISCV_EXT_FLAG_ENTRY ("zcmt", x_riscv_zc_subext, MASK_ZCMT),
  
-  RISCV_EXT_FLAG_ENTRY ("svinval", x_riscv_sv_subext, MASK_SVINVAL),
-  RISCV_EXT_FLAG_ENTRY ("svnapot", x_riscv_sv_subext, MASK_SVNAPOT),
-  RISCV_EXT_FLAG_ENTRY ("svvptc", x_riscv_sv_subext, MASK_SVVPTC),
+  RISCV_EXT_FLAG_ENTRY ("svinval",     x_riscv_sv_subext, MASK_SVINVAL),
+  RISCV_EXT_FLAG_ENTRY ("svnapot",     x_riscv_sv_subext, MASK_SVNAPOT),
+  RISCV_EXT_FLAG_ENTRY ("svvptc",      x_riscv_sv_subext, MASK_SVVPTC),
+  RISCV_EXT_FLAG_ENTRY ("svrsw60t59b", x_riscv_sv_subext, MASK_SVVPTC),

I think this should be MASK_SVRSW60T59B.

  
    RISCV_EXT_FLAG_ENTRY ("ztso", x_riscv_ztso_subext, MASK_ZTSO),
  
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 7515c8ea13d..4c6387ab709 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -472,6 +472,8 @@ Mask(SVNAPOT) Var(riscv_sv_subext)
  
  Mask(SVVPTC) Var(riscv_sv_subext)
  
+Mask(SVRSW60T59B) Var(riscv_sv_subext)
+
  TargetVariable
  int riscv_ztso_subext
  
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 0c7adc039b5..5adc27b45e0 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi

This file is missing from the ChangeLog.

@@ -31188,6 +31188,14 @@ to @samp{zvks} and @samp{zvkg}.
  @tab 1.0
  @tab Page-based memory types extension.
  
+@item svvptc
+@tab 1.0
+@tab Obviating Memory-Management Instructions after Marking PTEs Valid 
extension.

Adding missing documentation for svvptc seems unrelated, so may be 
better as a separate patch.

Thanks,
Craig

+
+@item svrsw60t59b
+@tab 1.0
+@tab PTE Reserved-for-Software Bits 60-59 extension.
+
  @item xcvmac
  @tab 1.0
  @tab Core-V multiply-accumulate extension.
diff --git a/gcc/testsuite/gcc.target/riscv/arch-45.c 
b/gcc/testsuite/gcc.target/riscv/arch-45.c
new file mode 100644
index 00000000000..fe3ee441d49
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-45.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_svrsw60t59b -mabi=lp64" } */
+int foo()
+{
+}