On 18/02/2025 08:37, Christophe Lyon wrote: > As discussed in the PR, removing the inner 'fix:HF/SD/DF' fixes the > problem, like other targets do. >
The double-'fix' idiom was introduced in https://gcc.gnu.org/pipermail/gcc-patches/2003-March/098380.html to address target/5985. Certainly at the time it seems that FIX had two meanings depending on the mode. If the target was a floating point mode it did a truncation operation with rounding. If it was an integer mode it did trucation with unspecified rounding. But the manual doesn't seem to mention FIX:<int_mode> (at least not now), so I'm wondering if something has been lost somewhere along the line. Anyway, I'm not sure this is right yet. R. > gcc/ChangeLog: > > PR rtl-optimization/117712 > * config/arm/arm.md (fix_trunchfsi2): Remove inner fix:HF. > (fix_trunchfdi2): Likewise. > (fix_truncsfsi2): Remove inner fix:SF. > (fix_truncdfsi2): Remove inner fix:DF. > * config/arm/vfp.md (truncsisf2_vfp): remove inner fix:SF. > (truncsidf2_vfp): Remove inner fix:DF. > (fixuns_truncsfsi2): Remove inner fix:SF. > (fixuns_truncdfsi2): Remove inner fix:DF. > > gcc/testsuite/ChangeLog: > > PR rtl-optimization/117712 > * gcc.target/arm/pr117712-df.c: New test. > * gcc.target/arm/pr117712-hf-di.c: New test. > * gcc.target/arm/pr117712-hf.c: New test. > * gcc.target/arm/pr117712-sf.c: New test. > --- > gcc/config/arm/arm.md | 8 ++++---- > gcc/config/arm/vfp.md | 8 ++++---- > gcc/testsuite/gcc.target/arm/pr117712-df.c | 10 ++++++++++ > gcc/testsuite/gcc.target/arm/pr117712-hf-di.c | 10 ++++++++++ > gcc/testsuite/gcc.target/arm/pr117712-hf.c | 10 ++++++++++ > gcc/testsuite/gcc.target/arm/pr117712-sf.c | 10 ++++++++++ > 6 files changed, 48 insertions(+), 8 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/arm/pr117712-df.c > create mode 100644 gcc/testsuite/gcc.target/arm/pr117712-hf-di.c > create mode 100644 gcc/testsuite/gcc.target/arm/pr117712-hf.c > create mode 100644 gcc/testsuite/gcc.target/arm/pr117712-sf.c > > diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md > index 442d86b9329..ed0d0da2e63 100644 > --- a/gcc/config/arm/arm.md > +++ b/gcc/config/arm/arm.md > @@ -5477,7 +5477,7 @@ (define_expand "floatsidf2" > > (define_expand "fix_trunchfsi2" > [(set (match_operand:SI 0 "general_operand") > - (fix:SI (fix:HF (match_operand:HF 1 "general_operand"))))] > + (fix:SI (match_operand:HF 1 "general_operand")))] > "TARGET_EITHER" > " > { > @@ -5489,7 +5489,7 @@ (define_expand "fix_trunchfsi2" > > (define_expand "fix_trunchfdi2" > [(set (match_operand:DI 0 "general_operand") > - (fix:DI (fix:HF (match_operand:HF 1 "general_operand"))))] > + (fix:DI (match_operand:HF 1 "general_operand")))] > "TARGET_EITHER" > " > { > @@ -5501,14 +5501,14 @@ (define_expand "fix_trunchfdi2" > > (define_expand "fix_truncsfsi2" > [(set (match_operand:SI 0 "s_register_operand") > - (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand"))))] > + (fix:SI (match_operand:SF 1 "s_register_operand")))] > "TARGET_32BIT && TARGET_HARD_FLOAT" > " > ") > > (define_expand "fix_truncdfsi2" > [(set (match_operand:SI 0 "s_register_operand") > - (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand"))))] > + (fix:SI (match_operand:DF 1 "s_register_operand")))] > "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE" > " > ") > diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md > index 379f5f7b3dc..0ef019b1727 100644 > --- a/gcc/config/arm/vfp.md > +++ b/gcc/config/arm/vfp.md > @@ -1508,7 +1508,7 @@ (define_insn "truncsfhf2" > > (define_insn "*truncsisf2_vfp" > [(set (match_operand:SI 0 "s_register_operand" "=t") > - (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))] > + (fix:SI (match_operand:SF 1 "s_register_operand" "t")))] > "TARGET_32BIT && TARGET_HARD_FLOAT" > "vcvt%?.s32.f32\\t%0, %1" > [(set_attr "predicable" "yes") > @@ -1517,7 +1517,7 @@ (define_insn "*truncsisf2_vfp" > > (define_insn "*truncsidf2_vfp" > [(set (match_operand:SI 0 "s_register_operand" "=t") > - (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "w"))))] > + (fix:SI (match_operand:DF 1 "s_register_operand" "w")))] > "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" > "vcvt%?.s32.f64\\t%0, %P1" > [(set_attr "predicable" "yes") > @@ -1527,7 +1527,7 @@ (define_insn "*truncsidf2_vfp" > > (define_insn "fixuns_truncsfsi2" > [(set (match_operand:SI 0 "s_register_operand" "=t") > - (unsigned_fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" > "t"))))] > + (unsigned_fix:SI (match_operand:SF 1 "s_register_operand" "t")))] > "TARGET_32BIT && TARGET_HARD_FLOAT" > "vcvt%?.u32.f32\\t%0, %1" > [(set_attr "predicable" "yes") > @@ -1536,7 +1536,7 @@ (define_insn "fixuns_truncsfsi2" > > (define_insn "fixuns_truncdfsi2" > [(set (match_operand:SI 0 "s_register_operand" "=t") > - (unsigned_fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" > "t"))))] > + (unsigned_fix:SI (match_operand:DF 1 "s_register_operand" "t")))] > "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" > "vcvt%?.u32.f64\\t%0, %P1" > [(set_attr "predicable" "yes") > diff --git a/gcc/testsuite/gcc.target/arm/pr117712-df.c > b/gcc/testsuite/gcc.target/arm/pr117712-df.c > new file mode 100644 > index 00000000000..534f2e4ed1d > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/pr117712-df.c > @@ -0,0 +1,10 @@ > +/* { dg-do assemble } */ > +/* { dg-options "-O2 -ffast-math" } */ > + > +int bCTUInfo; > +void compressInterCU_rd5_6(int qp) { > + if (bCTUInfo) > + qp = 0.96 * qp; > + for (;;) > + compressInterCU_rd5_6(qp); > +} > diff --git a/gcc/testsuite/gcc.target/arm/pr117712-hf-di.c > b/gcc/testsuite/gcc.target/arm/pr117712-hf-di.c > new file mode 100644 > index 00000000000..ea5ee0c8342 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/pr117712-hf-di.c > @@ -0,0 +1,10 @@ > +/* { dg-do assemble } */ > +/* { dg-options "-O2 -ffast-math -mfp16-format=ieee" } */ > + > +long long bCTUInfo; > +void compressInterCU_rd5_6(long long qp) { > + if (bCTUInfo) > + qp = 0.96f16 * qp; > + for (;;) > + compressInterCU_rd5_6(qp); > +} > diff --git a/gcc/testsuite/gcc.target/arm/pr117712-hf.c > b/gcc/testsuite/gcc.target/arm/pr117712-hf.c > new file mode 100644 > index 00000000000..d11c2cf749c > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/pr117712-hf.c > @@ -0,0 +1,10 @@ > +/* { dg-do assemble } */ > +/* { dg-options "-O2 -ffast-math -mfp16-format=ieee" } */ > + > +int bCTUInfo; > +void compressInterCU_rd5_6(int qp) { > + if (bCTUInfo) > + qp = 0.96f16 * qp; > + for (;;) > + compressInterCU_rd5_6(qp); > +} > diff --git a/gcc/testsuite/gcc.target/arm/pr117712-sf.c > b/gcc/testsuite/gcc.target/arm/pr117712-sf.c > new file mode 100644 > index 00000000000..744bad5de75 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/pr117712-sf.c > @@ -0,0 +1,10 @@ > +/* { dg-do assemble } */ > +/* { dg-options "-O2 -ffast-math" } */ > + > +int bCTUInfo; > +void compressInterCU_rd5_6(int qp) { > + if (bCTUInfo) > + qp = 0.96f * qp; > + for (;;) > + compressInterCU_rd5_6(qp); > +}
