> As described below, the patch also shows no change to AArch64 SPEC2017
> scores. I'm afraid I'll need help from x86 folks to do performance
> testing there.
I will look into this over weekend. I can write x86 version of the
hooks. Though in earlier email you mentioned you hacked up something, so
if you can share it with me, perhaps I can start from there.
> +/* Implement TARGET_CALLEE_SAVE_COST. */
> +static int
> +aarch64_callee_save_cost (spill_cost_type spill_type, unsigned int regno,
> + machine_mode mode, unsigned int nregs, int mem_cost,
> + const HARD_REG_SET &callee_saved_regs,
> + bool existing_spill_p)
> +{
I suppose here we only want to adjust load or save cost by 1 to account
for shorter push/pop operation...
> +
> +/* Implement TARGET_FRAME_ALLOCATION_COST. */
> +static int
> +aarch64_frame_allocation_cost (frame_cost_type,
> + const HARD_REG_SET &callee_saved_regs)
And here see if the register save area will need allocation...
So it seems relatively easy to do...
Honza
