Like what we've done for {lsx_,lasx_x}v{add,sub,mul}l{ev,od}, use
special predicates and TImode RTL instead of hard-coded const vectors
and UNSPECs.
Also reorder two operands of the outer plus in the template, so combine
will recognize {x,}vadd + {x,}vmulw{ev,od} => {x,}vmaddw{ev,od}.
gcc/ChangeLog:
* config/loongarch/lasx.md (UNSPEC_LASX_XVMADDWEV): Remove.
(UNSPEC_LASX_XVMADDWEV2): Remove.
(UNSPEC_LASX_XVMADDWEV3): Remove.
(UNSPEC_LASX_XVMADDWOD): Remove.
(UNSPEC_LASX_XVMADDWOD2): Remove.
(UNSPEC_LASX_XVMADDWOD3): Remove.
(lasx_xvmaddwev_h_b<u>): Remove.
(lasx_xvmaddwev_w_h<u>): Remove.
(lasx_xvmaddwev_d_w<u>): Remove.
(lasx_xvmaddwev_q_d): Remove.
(lasx_xvmaddwod_h_b<u>): Remove.
(lasx_xvmaddwod_w_h<u>): Remove.
(lasx_xvmaddwod_d_w<u>): Remove.
(lasx_xvmaddwod_q_d): Remove.
(lasx_xvmaddwev_q_du): Remove.
(lasx_xvmaddwod_q_du): Remove.
(lasx_xvmaddwev_h_bu_b): Remove.
(lasx_xvmaddwev_w_hu_h): Remove.
(lasx_xvmaddwev_d_wu_w): Remove.
(lasx_xvmaddwev_q_du_d): Remove.
(lasx_xvmaddwod_h_bu_b): Remove.
(lasx_xvmaddwod_w_hu_h): Remove.
(lasx_xvmaddwod_d_wu_w): Remove.
(lasx_xvmaddwod_q_du_d): Remove.
* config/loongarch/lsx.md (UNSPEC_LSX_VMADDWEV): Remove.
(UNSPEC_LSX_VMADDWEV2): Remove.
(UNSPEC_LSX_VMADDWEV3): Remove.
(UNSPEC_LSX_VMADDWOD): Remove.
(UNSPEC_LSX_VMADDWOD2): Remove.
(UNSPEC_LSX_VMADDWOD3): Remove.
(lsx_vmaddwev_h_b<u>): Remove.
(lsx_vmaddwev_w_h<u>): Remove.
(lsx_vmaddwev_d_w<u>): Remove.
(lsx_vmaddwev_q_d): Remove.
(lsx_vmaddwod_h_b<u>): Remove.
(lsx_vmaddwod_w_h<u>): Remove.
(lsx_vmaddwod_d_w<u>): Remove.
(lsx_vmaddwod_q_d): Remove.
(lsx_vmaddwev_q_du): Remove.
(lsx_vmaddwod_q_du): Remove.
(lsx_vmaddwev_h_bu_b): Remove.
(lsx_vmaddwev_w_hu_h): Remove.
(lsx_vmaddwev_d_wu_w): Remove.
(lsx_vmaddwev_q_du_d): Remove.
(lsx_vmaddwod_h_bu_b): Remove.
(lsx_vmaddwod_w_hu_h): Remove.
(lsx_vmaddwod_d_wu_w): Remove.
(lsx_vmaddwod_q_du_d): Remove.
* config/loongarch/simd.md (simd_maddw_evod_<mode>_<su>):
New define_insn.
(<simd_isa>_<x>vmaddw<ev_od>_<simdfmt_w>_<simdfmt><u>): New
define_expand.
(simd_maddw_evod_<mode>_hetero): New define_insn.
(<simd_isa>_<x>vmaddw<ev_od>_<simdfmt_w>_<simdfmt>u_<simdfmt>):
New define_expand.
(<simd_isa>_maddw<ev_od>_q_d<u>_punned): New define_expand.
(<simd_isa>_maddw<ev_od>_q_du_d_punned): New define_expand.
* config/loongarch/loongarch-builtins.cc
(CODE_FOR_lsx_vmaddwev_q_d): Define as a macro to override it
with the punned expand.
(CODE_FOR_lsx_vmaddwev_q_du): Likewise.
(CODE_FOR_lsx_vmaddwev_q_du_d): Likewise.
(CODE_FOR_lsx_vmaddwod_q_d): Likewise.
(CODE_FOR_lsx_vmaddwod_q_du): Likewise.
(CODE_FOR_lsx_vmaddwod_q_du_d): Likewise.
(CODE_FOR_lasx_xvmaddwev_q_d): Likewise.
(CODE_FOR_lasx_xvmaddwev_q_du): Likewise.
(CODE_FOR_lasx_xvmaddwev_q_du_d): Likewise.
(CODE_FOR_lasx_xvmaddwod_q_d): Likewise.
(CODE_FOR_lasx_xvmaddwod_q_du): Likewise.
(CODE_FOR_lasx_xvmaddwod_q_du_d): Likewise.
---
gcc/config/loongarch/lasx.md | 400 ---------------------
gcc/config/loongarch/loongarch-builtins.cc | 14 +
gcc/config/loongarch/lsx.md | 320 -----------------
gcc/config/loongarch/simd.md | 104 ++++++
4 files changed, 118 insertions(+), 720 deletions(-)
diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md
index 1dc11840187..4ac85b7fcf9 100644
--- a/gcc/config/loongarch/lasx.md
+++ b/gcc/config/loongarch/lasx.md
@@ -94,12 +94,6 @@ (define_c_enum "unspec" [
UNSPEC_LASX_XVPERMI_Q
UNSPEC_LASX_XVPERMI_D
- UNSPEC_LASX_XVMADDWEV
- UNSPEC_LASX_XVMADDWEV2
- UNSPEC_LASX_XVMADDWEV3
- UNSPEC_LASX_XVMADDWOD
- UNSPEC_LASX_XVMADDWOD2
- UNSPEC_LASX_XVMADDWOD3
UNSPEC_LASX_XVADD_Q
UNSPEC_LASX_XVSUB_Q
UNSPEC_LASX_XVREPLVE
@@ -3122,400 +3116,6 @@ (define_insn "lasx_xvldrepl_<lasxfmt_f>_insn_0"
(set_attr "mode" "<MODE>")
(set_attr "length" "4")])
-;;XVMADDWEV.H.B XVMADDWEV.H.BU
-(define_insn "lasx_xvmaddwev_h_b<u>"
- [(set (match_operand:V16HI 0 "register_operand" "=f")
- (plus:V16HI
- (match_operand:V16HI 1 "register_operand" "0")
- (mult:V16HI
- (any_extend:V16HI
- (vec_select:V16QI
- (match_operand:V32QI 2 "register_operand" "%f")
- (parallel [(const_int 0) (const_int 2)
- (const_int 4) (const_int 6)
- (const_int 8) (const_int 10)
- (const_int 12) (const_int 14)
- (const_int 16) (const_int 18)
- (const_int 20) (const_int 22)
- (const_int 24) (const_int 26)
- (const_int 28) (const_int 30)])))
- (any_extend:V16HI
- (vec_select:V16QI
- (match_operand:V32QI 3 "register_operand" "f")
- (parallel [(const_int 0) (const_int 2)
- (const_int 4) (const_int 6)
- (const_int 8) (const_int 10)
- (const_int 12) (const_int 14)
- (const_int 16) (const_int 18)
- (const_int 20) (const_int 22)
- (const_int 24) (const_int 26)
- (const_int 28) (const_int 30)]))))))]
- "ISA_HAS_LASX"
- "xvmaddwev.h.b<u>\t%u0,%u2,%u3"
- [(set_attr "type" "simd_fmadd")
- (set_attr "mode" "V16HI")])
-
-;;XVMADDWEV.W.H XVMADDWEV.W.HU
-(define_insn "lasx_xvmaddwev_w_h<u>"
- [(set (match_operand:V8SI 0 "register_operand" "=f")
- (plus:V8SI
- (match_operand:V8SI 1 "register_operand" "0")
- (mult:V8SI
- (any_extend:V8SI
- (vec_select:V8HI
- (match_operand:V16HI 2 "register_operand" "%f")
- (parallel [(const_int 0) (const_int 2)
- (const_int 4) (const_int 6)
- (const_int 8) (const_int 10)
- (const_int 12) (const_int 14)])))
- (any_extend:V8SI
- (vec_select:V8HI
- (match_operand:V16HI 3 "register_operand" "f")
- (parallel [(const_int 0) (const_int 2)
- (const_int 4) (const_int 6)
- (const_int 8) (const_int 10)
- (const_int 12) (const_int 14)]))))))]
- "ISA_HAS_LASX"
- "xvmaddwev.w.h<u>\t%u0,%u2,%u3"
- [(set_attr "type" "simd_fmadd")
- (set_attr "mode" "V8SI")])
-
-;;XVMADDWEV.D.W XVMADDWEV.D.WU
-(define_insn "lasx_xvmaddwev_d_w<u>"
- [(set (match_operand:V4DI 0 "register_operand" "=f")
- (plus:V4DI
- (match_operand:V4DI 1 "register_operand" "0")
- (mult:V4DI
- (any_extend:V4DI
- (vec_select:V4SI
- (match_operand:V8SI 2 "register_operand" "%f")
- (parallel [(const_int 0) (const_int 2)
- (const_int 4) (const_int 6)])))
- (any_extend:V4DI
- (vec_select:V4SI
- (match_operand:V8SI 3 "register_operand" "f")
- (parallel [(const_int 0) (const_int 2)
- (const_int 4) (const_int 6)]))))))]
- "ISA_HAS_LASX"
- "xvmaddwev.d.w<u>\t%u0,%u2,%u3"
- [(set_attr "type" "simd_fmadd")
- (set_attr "mode" "V4DI")])
-
-;;XVMADDWEV.Q.D
-;;TODO2
-(define_insn "lasx_xvmaddwev_q_d"
- [(set (match_operand:V4DI 0 "register_operand" "=f")
- (unspec:V4DI [(match_operand:V4DI 1 "register_operand" "0")
- (match_operand:V4DI 2 "register_operand" "f")
- (match_operand:V4DI 3 "register_operand" "f")]
- UNSPEC_LASX_XVMADDWEV))]
- "ISA_HAS_LASX"
- "xvmaddwev.q.d\t%u0,%u2,%u3"
- [(set_attr "type" "simd_int_arith")
- (set_attr "mode" "V4DI")])
-
-;;XVMADDWOD.H.B XVMADDWOD.H.BU
-(define_insn "lasx_xvmaddwod_h_b<u>"
- [(set (match_operand:V16HI 0 "register_operand" "=f")
- (plus:V16HI
- (match_operand:V16HI 1 "register_operand" "0")
- (mult:V16HI
- (any_extend:V16HI
- (vec_select:V16QI
- (match_operand:V32QI 2 "register_operand" "%f")
- (parallel [(const_int 1) (const_int 3)
- (const_int 5) (const_int 7)
- (const_int 9) (const_int 11)
- (const_int 13) (const_int 15)
- (const_int 17) (const_int 19)
- (const_int 21) (const_int 23)
- (const_int 25) (const_int 27)
- (const_int 29) (const_int 31)])))
- (any_extend:V16HI
- (vec_select:V16QI
- (match_operand:V32QI 3 "register_operand" "f")
- (parallel [(const_int 1) (const_int 3)
- (const_int 5) (const_int 7)
- (const_int 9) (const_int 11)
- (const_int 13) (const_int 15)
- (const_int 17) (const_int 19)
- (const_int 21) (const_int 23)
- (const_int 25) (const_int 27)
- (const_int 29) (const_int 31)]))))))]
- "ISA_HAS_LASX"
- "xvmaddwod.h.b<u>\t%u0,%u2,%u3"
- [(set_attr "type" "simd_fmadd")
- (set_attr "mode" "V16HI")])
-
-;;XVMADDWOD.W.H XVMADDWOD.W.HU
-(define_insn "lasx_xvmaddwod_w_h<u>"
- [(set (match_operand:V8SI 0 "register_operand" "=f")
- (plus:V8SI
- (match_operand:V8SI 1 "register_operand" "0")
- (mult:V8SI
- (any_extend:V8SI
- (vec_select:V8HI
- (match_operand:V16HI 2 "register_operand" "%f")
- (parallel [(const_int 1) (const_int 3)
- (const_int 5) (const_int 7)
- (const_int 9) (const_int 11)
- (const_int 13) (const_int 15)])))
- (any_extend:V8SI
- (vec_select:V8HI
- (match_operand:V16HI 3 "register_operand" "f")
- (parallel [(const_int 1) (const_int 3)
- (const_int 5) (const_int 7)
- (const_int 9) (const_int 11)
- (const_int 13) (const_int 15)]))))))]
- "ISA_HAS_LASX"
- "xvmaddwod.w.h<u>\t%u0,%u2,%u3"
- [(set_attr "type" "simd_fmadd")
- (set_attr "mode" "V8SI")])
-
-;;XVMADDWOD.D.W XVMADDWOD.D.WU
-(define_insn "lasx_xvmaddwod_d_w<u>"
- [(set (match_operand:V4DI 0 "register_operand" "=f")
- (plus:V4DI
- (match_operand:V4DI 1 "register_operand" "0")
- (mult:V4DI
- (any_extend:V4DI
- (vec_select:V4SI
- (match_operand:V8SI 2 "register_operand" "%f")
- (parallel [(const_int 1) (const_int 3)
- (const_int 5) (const_int 7)])))
- (any_extend:V4DI
- (vec_select:V4SI
- (match_operand:V8SI 3 "register_operand" "f")
- (parallel [(const_int 1) (const_int 3)
- (const_int 5) (const_int 7)]))))))]
- "ISA_HAS_LASX"
- "xvmaddwod.d.w<u>\t%u0,%u2,%u3"
- [(set_attr "type" "simd_fmadd")
- (set_attr "mode" "V4DI")])
-
-;;XVMADDWOD.Q.D
-;;TODO2
-(define_insn "lasx_xvmaddwod_q_d"
- [(set (match_operand:V4DI 0 "register_operand" "=f")
- (unspec:V4DI [(match_operand:V4DI 1 "register_operand" "0")
- (match_operand:V4DI 2 "register_operand" "f")
- (match_operand:V4DI 3 "register_operand" "f")]
- UNSPEC_LASX_XVMADDWOD))]
- "ISA_HAS_LASX"
- "xvmaddwod.q.d\t%u0,%u2,%u3"
- [(set_attr "type" "simd_int_arith")
- (set_attr "mode" "V4DI")])
-
-;;XVMADDWEV.Q.DU
-;;TODO2
-(define_insn "lasx_xvmaddwev_q_du"
- [(set (match_operand:V4DI 0 "register_operand" "=f")
- (unspec:V4DI [(match_operand:V4DI 1 "register_operand" "0")
- (match_operand:V4DI 2 "register_operand" "f")
- (match_operand:V4DI 3 "register_operand" "f")]
- UNSPEC_LASX_XVMADDWEV2))]
- "ISA_HAS_LASX"
- "xvmaddwev.q.du\t%u0,%u2,%u3"
- [(set_attr "type" "simd_int_arith")
- (set_attr "mode" "V4DI")])
-
-;;XVMADDWOD.Q.DU
-;;TODO2
-(define_insn "lasx_xvmaddwod_q_du"
- [(set (match_operand:V4DI 0 "register_operand" "=f")
- (unspec:V4DI [(match_operand:V4DI 1 "register_operand" "0")
- (match_operand:V4DI 2 "register_operand" "f")
- (match_operand:V4DI 3 "register_operand" "f")]
- UNSPEC_LASX_XVMADDWOD2))]
- "ISA_HAS_LASX"
- "xvmaddwod.q.du\t%u0,%u2,%u3"
- [(set_attr "type" "simd_int_arith")
- (set_attr "mode" "V4DI")])
-
-;;XVMADDWEV.H.BU.B
-(define_insn "lasx_xvmaddwev_h_bu_b"
- [(set (match_operand:V16HI 0 "register_operand" "=f")
- (plus:V16HI
- (match_operand:V16HI 1 "register_operand" "0")
- (mult:V16HI
- (zero_extend:V16HI
- (vec_select:V16QI
- (match_operand:V32QI 2 "register_operand" "%f")
- (parallel [(const_int 0) (const_int 2)
- (const_int 4) (const_int 6)
- (const_int 8) (const_int 10)
- (const_int 12) (const_int 14)
- (const_int 16) (const_int 18)
- (const_int 20) (const_int 22)
- (const_int 24) (const_int 26)
- (const_int 28) (const_int 30)])))
- (sign_extend:V16HI
- (vec_select:V16QI
- (match_operand:V32QI 3 "register_operand" "f")
- (parallel [(const_int 0) (const_int 2)
- (const_int 4) (const_int 6)
- (const_int 8) (const_int 10)
- (const_int 12) (const_int 14)
- (const_int 16) (const_int 18)
- (const_int 20) (const_int 22)
- (const_int 24) (const_int 26)
- (const_int 28) (const_int 30)]))))))]
- "ISA_HAS_LASX"
- "xvmaddwev.h.bu.b\t%u0,%u2,%u3"
- [(set_attr "type" "simd_fmadd")
- (set_attr "mode" "V16HI")])
-
-;;XVMADDWEV.W.HU.H
-(define_insn "lasx_xvmaddwev_w_hu_h"
- [(set (match_operand:V8SI 0 "register_operand" "=f")
- (plus:V8SI
- (match_operand:V8SI 1 "register_operand" "0")
- (mult:V8SI
- (zero_extend:V8SI
- (vec_select:V8HI
- (match_operand:V16HI 2 "register_operand" "%f")
- (parallel [(const_int 0) (const_int 2)
- (const_int 4) (const_int 6)
- (const_int 8) (const_int 10)
- (const_int 12) (const_int 14)])))
- (sign_extend:V8SI
- (vec_select:V8HI
- (match_operand:V16HI 3 "register_operand" "f")
- (parallel [(const_int 0) (const_int 2)
- (const_int 4) (const_int 6)
- (const_int 8) (const_int 10)
- (const_int 12) (const_int 14)]))))))]
- "ISA_HAS_LASX"
- "xvmaddwev.w.hu.h\t%u0,%u2,%u3"
- [(set_attr "type" "simd_fmadd")
- (set_attr "mode" "V8SI")])
-
-;;XVMADDWEV.D.WU.W
-(define_insn "lasx_xvmaddwev_d_wu_w"
- [(set (match_operand:V4DI 0 "register_operand" "=f")
- (plus:V4DI
- (match_operand:V4DI 1 "register_operand" "0")
- (mult:V4DI
- (zero_extend:V4DI
- (vec_select:V4SI
- (match_operand:V8SI 2 "register_operand" "%f")
- (parallel [(const_int 0) (const_int 2)
- (const_int 4) (const_int 6)])))
- (sign_extend:V4DI
- (vec_select:V4SI
- (match_operand:V8SI 3 "register_operand" "f")
- (parallel [(const_int 0) (const_int 2)
- (const_int 4) (const_int 6)]))))))]
- "ISA_HAS_LASX"
- "xvmaddwev.d.wu.w\t%u0,%u2,%u3"
- [(set_attr "type" "simd_fmadd")
- (set_attr "mode" "V4DI")])
-
-;;XVMADDWEV.Q.DU.D
-;;TODO2
-(define_insn "lasx_xvmaddwev_q_du_d"
- [(set (match_operand:V4DI 0 "register_operand" "=f")
- (unspec:V4DI [(match_operand:V4DI 1 "register_operand" "0")
- (match_operand:V4DI 2 "register_operand" "f")
- (match_operand:V4DI 3 "register_operand" "f")]
- UNSPEC_LASX_XVMADDWEV3))]
- "ISA_HAS_LASX"
- "xvmaddwev.q.du.d\t%u0,%u2,%u3"
- [(set_attr "type" "simd_int_arith")
- (set_attr "mode" "V4DI")])
-
-;;XVMADDWOD.H.BU.B
-(define_insn "lasx_xvmaddwod_h_bu_b"
- [(set (match_operand:V16HI 0 "register_operand" "=f")
- (plus:V16HI
- (match_operand:V16HI 1 "register_operand" "0")
- (mult:V16HI
- (zero_extend:V16HI
- (vec_select:V16QI
- (match_operand:V32QI 2 "register_operand" "%f")
- (parallel [(const_int 1) (const_int 3)
- (const_int 5) (const_int 7)
- (const_int 9) (const_int 11)
- (const_int 13) (const_int 15)
- (const_int 17) (const_int 19)
- (const_int 21) (const_int 23)
- (const_int 25) (const_int 27)
- (const_int 29) (const_int 31)])))
- (sign_extend:V16HI
- (vec_select:V16QI
- (match_operand:V32QI 3 "register_operand" "f")
- (parallel [(const_int 1) (const_int 3)
- (const_int 5) (const_int 7)
- (const_int 9) (const_int 11)
- (const_int 13) (const_int 15)
- (const_int 17) (const_int 19)
- (const_int 21) (const_int 23)
- (const_int 25) (const_int 27)
- (const_int 29) (const_int 31)]))))))]
- "ISA_HAS_LASX"
- "xvmaddwod.h.bu.b\t%u0,%u2,%u3"
- [(set_attr "type" "simd_fmadd")
- (set_attr "mode" "V16HI")])
-
-;;XVMADDWOD.W.HU.H
-(define_insn "lasx_xvmaddwod_w_hu_h"
- [(set (match_operand:V8SI 0 "register_operand" "=f")
- (plus:V8SI
- (match_operand:V8SI 1 "register_operand" "0")
- (mult:V8SI
- (zero_extend:V8SI
- (vec_select:V8HI
- (match_operand:V16HI 2 "register_operand" "%f")
- (parallel [(const_int 1) (const_int 3)
- (const_int 5) (const_int 7)
- (const_int 9) (const_int 11)
- (const_int 13) (const_int 15)])))
- (sign_extend:V8SI
- (vec_select:V8HI
- (match_operand:V16HI 3 "register_operand" "f")
- (parallel [(const_int 1) (const_int 3)
- (const_int 5) (const_int 7)
- (const_int 9) (const_int 11)
- (const_int 13) (const_int 15)]))))))]
- "ISA_HAS_LASX"
- "xvmaddwod.w.hu.h\t%u0,%u2,%u3"
- [(set_attr "type" "simd_fmadd")
- (set_attr "mode" "V8SI")])
-
-;;XVMADDWOD.D.WU.W
-(define_insn "lasx_xvmaddwod_d_wu_w"
- [(set (match_operand:V4DI 0 "register_operand" "=f")
- (plus:V4DI
- (match_operand:V4DI 1 "register_operand" "0")
- (mult:V4DI
- (zero_extend:V4DI
- (vec_select:V4SI
- (match_operand:V8SI 2 "register_operand" "%f")
- (parallel [(const_int 1) (const_int 3)
- (const_int 5) (const_int 7)])))
- (sign_extend:V4DI
- (vec_select:V4SI
- (match_operand:V8SI 3 "register_operand" "f")
- (parallel [(const_int 1) (const_int 3)
- (const_int 5) (const_int 7)]))))))]
- "ISA_HAS_LASX"
- "xvmaddwod.d.wu.w\t%u0,%u2,%u3"
- [(set_attr "type" "simd_fmadd")
- (set_attr "mode" "V4DI")])
-
-;;XVMADDWOD.Q.DU.D
-;;TODO2
-(define_insn "lasx_xvmaddwod_q_du_d"
- [(set (match_operand:V4DI 0 "register_operand" "=f")
- (unspec:V4DI [(match_operand:V4DI 1 "register_operand" "0")
- (match_operand:V4DI 2 "register_operand" "f")
- (match_operand:V4DI 3 "register_operand" "f")]
- UNSPEC_LASX_XVMADDWOD3))]
- "ISA_HAS_LASX"
- "xvmaddwod.q.du.d\t%u0,%u2,%u3"
- [(set_attr "type" "simd_int_arith")
- (set_attr "mode" "V4DI")])
-
;;XVADD.Q
;;TODO2
(define_insn "lasx_xvadd_q"
diff --git a/gcc/config/loongarch/loongarch-builtins.cc
b/gcc/config/loongarch/loongarch-builtins.cc
index a87e6273065..9493dedcab7 100644
--- a/gcc/config/loongarch/loongarch-builtins.cc
+++ b/gcc/config/loongarch/loongarch-builtins.cc
@@ -542,6 +542,13 @@ AVAIL_ALL (lasx_frecipe, ISA_HAS_LASX && ISA_HAS_FRECIPE)
#define CODE_FOR_lsx_vhsubw_q_d CODE_FOR_lsx_hsubw_q_d_punned
#define CODE_FOR_lsx_vhsubw_qu_du CODE_FOR_lsx_hsubw_qu_du_punned
+#define CODE_FOR_lsx_vmaddwev_q_d CODE_FOR_lsx_maddwev_q_d_punned
+#define CODE_FOR_lsx_vmaddwev_q_du CODE_FOR_lsx_maddwev_q_du_punned
+#define CODE_FOR_lsx_vmaddwev_q_du_d CODE_FOR_lsx_maddwev_q_du_d_punned
+#define CODE_FOR_lsx_vmaddwod_q_d CODE_FOR_lsx_maddwod_q_d_punned
+#define CODE_FOR_lsx_vmaddwod_q_du CODE_FOR_lsx_maddwod_q_du_punned
+#define CODE_FOR_lsx_vmaddwod_q_du_d CODE_FOR_lsx_maddwod_q_du_d_punned
+
/* LoongArch ASX define CODE_FOR_lasx_mxxx */
#define CODE_FOR_lasx_xvsadd_b CODE_FOR_ssaddv32qi3
#define CODE_FOR_lasx_xvsadd_h CODE_FOR_ssaddv16hi3
@@ -851,6 +858,13 @@ AVAIL_ALL (lasx_frecipe, ISA_HAS_LASX && ISA_HAS_FRECIPE)
#define CODE_FOR_lasx_xvhsubw_q_d CODE_FOR_lasx_hsubw_q_d_punned
#define CODE_FOR_lasx_xvhsubw_qu_du CODE_FOR_lasx_hsubw_qu_du_punned
+#define CODE_FOR_lasx_xvmaddwev_q_d CODE_FOR_lasx_maddwev_q_d_punned
+#define CODE_FOR_lasx_xvmaddwev_q_du CODE_FOR_lasx_maddwev_q_du_punned
+#define CODE_FOR_lasx_xvmaddwev_q_du_d CODE_FOR_lasx_maddwev_q_du_d_punned
+#define CODE_FOR_lasx_xvmaddwod_q_d CODE_FOR_lasx_maddwod_q_d_punned
+#define CODE_FOR_lasx_xvmaddwod_q_du CODE_FOR_lasx_maddwod_q_du_punned
+#define CODE_FOR_lasx_xvmaddwod_q_du_d CODE_FOR_lasx_maddwod_q_du_d_punned
+
static const struct loongarch_builtin_description loongarch_builtins[] = {
#define LARCH_MOVFCSR2GR 0
DIRECT_BUILTIN (movfcsr2gr, LARCH_USI_FTYPE_UQI, hard_float),
diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md
index 1783c24e635..c7df04c6389 100644
--- a/gcc/config/loongarch/lsx.md
+++ b/gcc/config/loongarch/lsx.md
@@ -93,12 +93,6 @@ (define_c_enum "unspec" [
UNSPEC_LSX_VSTX
UNSPEC_LSX_VEXTL_QU_DU
UNSPEC_LSX_VSETEQZ_V
- UNSPEC_LSX_VMADDWEV
- UNSPEC_LSX_VMADDWEV2
- UNSPEC_LSX_VMADDWEV3
- UNSPEC_LSX_VMADDWOD
- UNSPEC_LSX_VMADDWOD2
- UNSPEC_LSX_VMADDWOD3
UNSPEC_LSX_VADD_Q
UNSPEC_LSX_VSUB_Q
UNSPEC_LSX_VEXTH_Q_D
@@ -3092,320 +3086,6 @@ (define_expand "ssadv16qi"
DONE;
})
-(define_insn "lsx_vmaddwev_d_w<u>"
- [(set (match_operand:V2DI 0 "register_operand" "=f")
- (plus:V2DI
- (match_operand:V2DI 1 "register_operand" "0")
- (mult:V2DI
- (any_extend:V2DI
- (vec_select:V2SI
- (match_operand:V4SI 2 "register_operand" "%f")
- (parallel [(const_int 0) (const_int 2)])))
- (any_extend:V2DI
- (vec_select:V2SI
- (match_operand:V4SI 3 "register_operand" "f")
- (parallel [(const_int 0) (const_int 2)]))))))]
- "ISA_HAS_LSX"
- "vmaddwev.d.w<u>\t%w0,%w2,%w3"
- [(set_attr "type" "simd_fmadd")
- (set_attr "mode" "V2DI")])
-
-(define_insn "lsx_vmaddwev_w_h<u>"
- [(set (match_operand:V4SI 0 "register_operand" "=f")
- (plus:V4SI
- (match_operand:V4SI 1 "register_operand" "0")
- (mult:V4SI
- (any_extend:V4SI
- (vec_select:V4HI
- (match_operand:V8HI 2 "register_operand" "%f")
- (parallel [(const_int 0) (const_int 2)
- (const_int 4) (const_int 6)])))
- (any_extend:V4SI
- (vec_select:V4HI
- (match_operand:V8HI 3 "register_operand" "f")
- (parallel [(const_int 0) (const_int 2)
- (const_int 4) (const_int 6)]))))))]
- "ISA_HAS_LSX"
- "vmaddwev.w.h<u>\t%w0,%w2,%w3"
- [(set_attr "type" "simd_fmadd")
- (set_attr "mode" "V4SI")])
-
-(define_insn "lsx_vmaddwev_h_b<u>"
- [(set (match_operand:V8HI 0 "register_operand" "=f")
- (plus:V8HI
- (match_operand:V8HI 1 "register_operand" "0")
- (mult:V8HI
- (any_extend:V8HI
- (vec_select:V8QI
- (match_operand:V16QI 2 "register_operand" "%f")
- (parallel [(const_int 0) (const_int 2)
- (const_int 4) (const_int 6)
- (const_int 8) (const_int 10)
- (const_int 12) (const_int 14)])))
- (any_extend:V8HI
- (vec_select:V8QI
- (match_operand:V16QI 3 "register_operand" "f")
- (parallel [(const_int 0) (const_int 2)
- (const_int 4) (const_int 6)
- (const_int 8) (const_int 10)
- (const_int 12) (const_int 14)]))))))]
- "ISA_HAS_LSX"
- "vmaddwev.h.b<u>\t%w0,%w2,%w3"
- [(set_attr "type" "simd_fmadd")
- (set_attr "mode" "V8HI")])
-
-(define_insn "lsx_vmaddwod_d_w<u>"
- [(set (match_operand:V2DI 0 "register_operand" "=f")
- (plus:V2DI
- (match_operand:V2DI 1 "register_operand" "0")
- (mult:V2DI
- (any_extend:V2DI
- (vec_select:V2SI
- (match_operand:V4SI 2 "register_operand" "%f")
- (parallel [(const_int 1) (const_int 3)])))
- (any_extend:V2DI
- (vec_select:V2SI
- (match_operand:V4SI 3 "register_operand" "f")
- (parallel [(const_int 1) (const_int 3)]))))))]
- "ISA_HAS_LSX"
- "vmaddwod.d.w<u>\t%w0,%w2,%w3"
- [(set_attr "type" "simd_fmadd")
- (set_attr "mode" "V2DI")])
-
-(define_insn "lsx_vmaddwod_w_h<u>"
- [(set (match_operand:V4SI 0 "register_operand" "=f")
- (plus:V4SI
- (match_operand:V4SI 1 "register_operand" "0")
- (mult:V4SI
- (any_extend:V4SI
- (vec_select:V4HI
- (match_operand:V8HI 2 "register_operand" "%f")
- (parallel [(const_int 1) (const_int 3)
- (const_int 5) (const_int 7)])))
- (any_extend:V4SI
- (vec_select:V4HI
- (match_operand:V8HI 3 "register_operand" "f")
- (parallel [(const_int 1) (const_int 3)
- (const_int 5) (const_int 7)]))))))]
- "ISA_HAS_LSX"
- "vmaddwod.w.h<u>\t%w0,%w2,%w3"
- [(set_attr "type" "simd_fmadd")
- (set_attr "mode" "V4SI")])
-
-(define_insn "lsx_vmaddwod_h_b<u>"
- [(set (match_operand:V8HI 0 "register_operand" "=f")
- (plus:V8HI
- (match_operand:V8HI 1 "register_operand" "0")
- (mult:V8HI
- (any_extend:V8HI
- (vec_select:V8QI
- (match_operand:V16QI 2 "register_operand" "%f")
- (parallel [(const_int 1) (const_int 3)
- (const_int 5) (const_int 7)
- (const_int 9) (const_int 11)
- (const_int 13) (const_int 15)])))
- (any_extend:V8HI
- (vec_select:V8QI
- (match_operand:V16QI 3 "register_operand" "f")
- (parallel [(const_int 1) (const_int 3)
- (const_int 5) (const_int 7)
- (const_int 9) (const_int 11)
- (const_int 13) (const_int 15)]))))))]
- "ISA_HAS_LSX"
- "vmaddwod.h.b<u>\t%w0,%w2,%w3"
- [(set_attr "type" "simd_fmadd")
- (set_attr "mode" "V8HI")])
-
-(define_insn "lsx_vmaddwev_d_wu_w"
- [(set (match_operand:V2DI 0 "register_operand" "=f")
- (plus:V2DI
- (match_operand:V2DI 1 "register_operand" "0")
- (mult:V2DI
- (zero_extend:V2DI
- (vec_select:V2SI
- (match_operand:V4SI 2 "register_operand" "%f")
- (parallel [(const_int 0) (const_int 2)])))
- (sign_extend:V2DI
- (vec_select:V2SI
- (match_operand:V4SI 3 "register_operand" "f")
- (parallel [(const_int 0) (const_int 2)]))))))]
- "ISA_HAS_LSX"
- "vmaddwev.d.wu.w\t%w0,%w2,%w3"
- [(set_attr "type" "simd_fmadd")
- (set_attr "mode" "V2DI")])
-
-(define_insn "lsx_vmaddwev_w_hu_h"
- [(set (match_operand:V4SI 0 "register_operand" "=f")
- (plus:V4SI
- (match_operand:V4SI 1 "register_operand" "0")
- (mult:V4SI
- (zero_extend:V4SI
- (vec_select:V4HI
- (match_operand:V8HI 2 "register_operand" "%f")
- (parallel [(const_int 0) (const_int 2)
- (const_int 4) (const_int 6)])))
- (sign_extend:V4SI
- (vec_select:V4HI
- (match_operand:V8HI 3 "register_operand" "f")
- (parallel [(const_int 0) (const_int 2)
- (const_int 4) (const_int 6)]))))))]
- "ISA_HAS_LSX"
- "vmaddwev.w.hu.h\t%w0,%w2,%w3"
- [(set_attr "type" "simd_fmadd")
- (set_attr "mode" "V4SI")])
-
-(define_insn "lsx_vmaddwev_h_bu_b"
- [(set (match_operand:V8HI 0 "register_operand" "=f")
- (plus:V8HI
- (match_operand:V8HI 1 "register_operand" "0")
- (mult:V8HI
- (zero_extend:V8HI
- (vec_select:V8QI
- (match_operand:V16QI 2 "register_operand" "%f")
- (parallel [(const_int 0) (const_int 2)
- (const_int 4) (const_int 6)
- (const_int 8) (const_int 10)
- (const_int 12) (const_int 14)])))
- (sign_extend:V8HI
- (vec_select:V8QI
- (match_operand:V16QI 3 "register_operand" "f")
- (parallel [(const_int 0) (const_int 2)
- (const_int 4) (const_int 6)
- (const_int 8) (const_int 10)
- (const_int 12) (const_int 14)]))))))]
- "ISA_HAS_LSX"
- "vmaddwev.h.bu.b\t%w0,%w2,%w3"
- [(set_attr "type" "simd_fmadd")
- (set_attr "mode" "V8HI")])
-
-(define_insn "lsx_vmaddwod_d_wu_w"
- [(set (match_operand:V2DI 0 "register_operand" "=f")
- (plus:V2DI
- (match_operand:V2DI 1 "register_operand" "0")
- (mult:V2DI
- (zero_extend:V2DI
- (vec_select:V2SI
- (match_operand:V4SI 2 "register_operand" "%f")
- (parallel [(const_int 1) (const_int 3)])))
- (sign_extend:V2DI
- (vec_select:V2SI
- (match_operand:V4SI 3 "register_operand" "f")
- (parallel [(const_int 1) (const_int 3)]))))))]
- "ISA_HAS_LSX"
- "vmaddwod.d.wu.w\t%w0,%w2,%w3"
- [(set_attr "type" "simd_fmadd")
- (set_attr "mode" "V2DI")])
-
-(define_insn "lsx_vmaddwod_w_hu_h"
- [(set (match_operand:V4SI 0 "register_operand" "=f")
- (plus:V4SI
- (match_operand:V4SI 1 "register_operand" "0")
- (mult:V4SI
- (zero_extend:V4SI
- (vec_select:V4HI
- (match_operand:V8HI 2 "register_operand" "%f")
- (parallel [(const_int 1) (const_int 3)
- (const_int 5) (const_int 7)])))
- (sign_extend:V4SI
- (vec_select:V4HI
- (match_operand:V8HI 3 "register_operand" "f")
- (parallel [(const_int 1) (const_int 3)
- (const_int 5) (const_int 7)]))))))]
- "ISA_HAS_LSX"
- "vmaddwod.w.hu.h\t%w0,%w2,%w3"
- [(set_attr "type" "simd_fmadd")
- (set_attr "mode" "V4SI")])
-
-(define_insn "lsx_vmaddwod_h_bu_b"
- [(set (match_operand:V8HI 0 "register_operand" "=f")
- (plus:V8HI
- (match_operand:V8HI 1 "register_operand" "0")
- (mult:V8HI
- (zero_extend:V8HI
- (vec_select:V8QI
- (match_operand:V16QI 2 "register_operand" "%f")
- (parallel [(const_int 1) (const_int 3)
- (const_int 5) (const_int 7)
- (const_int 9) (const_int 11)
- (const_int 13) (const_int 15)])))
- (sign_extend:V8HI
- (vec_select:V8QI
- (match_operand:V16QI 3 "register_operand" "f")
- (parallel [(const_int 1) (const_int 3)
- (const_int 5) (const_int 7)
- (const_int 9) (const_int 11)
- (const_int 13) (const_int 15)]))))))]
- "ISA_HAS_LSX"
- "vmaddwod.h.bu.b\t%w0,%w2,%w3"
- [(set_attr "type" "simd_fmadd")
- (set_attr "mode" "V8HI")])
-
-(define_insn "lsx_vmaddwev_q_d"
- [(set (match_operand:V2DI 0 "register_operand" "=f")
- (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
- (match_operand:V2DI 2 "register_operand" "f")
- (match_operand:V2DI 3 "register_operand" "f")]
- UNSPEC_LSX_VMADDWEV))]
- "ISA_HAS_LSX"
- "vmaddwev.q.d\t%w0,%w2,%w3"
- [(set_attr "type" "simd_int_arith")
- (set_attr "mode" "V2DI")])
-
-(define_insn "lsx_vmaddwod_q_d"
- [(set (match_operand:V2DI 0 "register_operand" "=f")
- (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
- (match_operand:V2DI 2 "register_operand" "f")
- (match_operand:V2DI 3 "register_operand" "f")]
- UNSPEC_LSX_VMADDWOD))]
- "ISA_HAS_LSX"
- "vmaddwod.q.d\t%w0,%w2,%w3"
- [(set_attr "type" "simd_int_arith")
- (set_attr "mode" "V2DI")])
-
-(define_insn "lsx_vmaddwev_q_du"
- [(set (match_operand:V2DI 0 "register_operand" "=f")
- (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
- (match_operand:V2DI 2 "register_operand" "f")
- (match_operand:V2DI 3 "register_operand" "f")]
- UNSPEC_LSX_VMADDWEV2))]
- "ISA_HAS_LSX"
- "vmaddwev.q.du\t%w0,%w2,%w3"
- [(set_attr "type" "simd_int_arith")
- (set_attr "mode" "V2DI")])
-
-(define_insn "lsx_vmaddwod_q_du"
- [(set (match_operand:V2DI 0 "register_operand" "=f")
- (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
- (match_operand:V2DI 2 "register_operand" "f")
- (match_operand:V2DI 3 "register_operand" "f")]
- UNSPEC_LSX_VMADDWOD2))]
- "ISA_HAS_LSX"
- "vmaddwod.q.du\t%w0,%w2,%w3"
- [(set_attr "type" "simd_int_arith")
- (set_attr "mode" "V2DI")])
-
-(define_insn "lsx_vmaddwev_q_du_d"
- [(set (match_operand:V2DI 0 "register_operand" "=f")
- (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
- (match_operand:V2DI 2 "register_operand" "f")
- (match_operand:V2DI 3 "register_operand" "f")]
- UNSPEC_LSX_VMADDWEV3))]
- "ISA_HAS_LSX"
- "vmaddwev.q.du.d\t%w0,%w2,%w3"
- [(set_attr "type" "simd_int_arith")
- (set_attr "mode" "V2DI")])
-
-(define_insn "lsx_vmaddwod_q_du_d"
- [(set (match_operand:V2DI 0 "register_operand" "=f")
- (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
- (match_operand:V2DI 2 "register_operand" "f")
- (match_operand:V2DI 3 "register_operand" "f")]
- UNSPEC_LSX_VMADDWOD3))]
- "ISA_HAS_LSX"
- "vmaddwod.q.du.d\t%w0,%w2,%w3"
- [(set_attr "type" "simd_int_arith")
- (set_attr "mode" "V2DI")])
-
(define_insn "lsx_vadd_q"
[(set (match_operand:V2DI 0 "register_operand" "=f")
(unspec:V2DI [(match_operand:V2DI 1 "register_operand" "f")
diff --git a/gcc/config/loongarch/simd.md b/gcc/config/loongarch/simd.md
index 5c2cad44ef0..1bf273d3f44 100644
--- a/gcc/config/loongarch/simd.md
+++ b/gcc/config/loongarch/simd.md
@@ -704,6 +704,77 @@ (define_expand
"<simd_isa>_<x>vh<optab>w_<simdfmt_w><u>_<simdfmt><u>"
DONE;
})
+(define_insn "simd_maddw_evod_<mode>_<su>"
+ [(set (match_operand:<WVEC_HALF> 0 "register_operand" "=f")
+ (plus:<WVEC_HALF>
+ (mult:<WVEC_HALF>
+ (vec_select:<WVEC_HALF>
+ (any_extend:<WVEC>
+ (match_operand:IVEC 2 "register_operand" "f"))
+ (match_operand:<WVEC> 4 "vect_par_cnst_even_or_odd_half"))
+ (vec_select:<WVEC_HALF>
+ (any_extend:<WVEC>
+ (match_operand:IVEC 3 "register_operand" "f"))
+ (match_dup 4)))
+ (match_operand:<WVEC_HALF> 1 "register_operand" "0")))]
+ ""
+ "<x>vmaddw%O4.<simdfmt_w>.<simdfmt><u>\t%<wu>0,%<wu>2,%<wu>3"
+ [(set_attr "type" "simd_int_arith")
+ (set_attr "mode" "<WVEC_HALF>")])
+
+(define_expand "<simd_isa>_<x>vmaddw<ev_od>_<simdfmt_w>_<simdfmt><u>"
+ [(match_operand:<WVEC_HALF> 0 "register_operand" "=f")
+ (match_operand:<WVEC_HALF> 1 "register_operand" " 0")
+ (match_operand:IVEC 2 "register_operand" " f")
+ (match_operand:IVEC 3 "register_operand" " f")
+ (any_extend (const_int 0))
+ (const_int zero_one)]
+ ""
+{
+ int nelts = GET_MODE_NUNITS (<WVEC_HALF>mode);
+ rtx op4 = loongarch_gen_stepped_int_parallel (nelts, <zero_one>, 2);
+ rtx insn = gen_simd_maddw_evod_<mode>_<su> (operands[0], operands[1],
+ operands[2], operands[3],
+ op4);
+ emit_insn (insn);
+ DONE;
+})
+
+(define_insn "simd_maddw_evod_<mode>_hetero"
+ [(set (match_operand:<WVEC_HALF> 0 "register_operand" "=f")
+ (plus:<WVEC_HALF>
+ (mult:<WVEC_HALF>
+ (vec_select:<WVEC_HALF>
+ (zero_extend:<WVEC>
+ (match_operand:IVEC 2 "register_operand" "f"))
+ (match_operand:<WVEC> 4 "vect_par_cnst_even_or_odd_half"))
+ (vec_select:<WVEC_HALF>
+ (sign_extend:<WVEC>
+ (match_operand:IVEC 3 "register_operand" "f"))
+ (match_dup 4)))
+ (match_operand:<WVEC_HALF> 1 "register_operand" "0")))]
+ ""
+ "<x>vmaddw%O4.<simdfmt_w>.<simdfmt>u.<simdfmt>\t%<wu>0,%<wu>2,%<wu>3"
+ [(set_attr "type" "simd_int_arith")
+ (set_attr "mode" "<WVEC_HALF>")])
+
+(define_expand "<simd_isa>_<x>vmaddw<ev_od>_<simdfmt_w>_<simdfmt>u_<simdfmt>"
+ [(match_operand:<WVEC_HALF> 0 "register_operand" "=f")
+ (match_operand:<WVEC_HALF> 1 "register_operand" " 0")
+ (match_operand:IVEC 2 "register_operand" " f")
+ (match_operand:IVEC 3 "register_operand" " f")
+ (const_int zero_one)]
+ ""
+{
+ int nelts = GET_MODE_NUNITS (<WVEC_HALF>mode);
+ rtx op4 = loongarch_gen_stepped_int_parallel (nelts, <zero_one>, 2);
+ rtx insn = gen_simd_maddw_evod_<mode>_hetero (operands[0], operands[1],
+ operands[2], operands[3],
+ op4);
+ emit_insn (insn);
+ DONE;
+})
+
; For "historical" reason we need a punned version of q_d variants.
(define_mode_iterator DIVEC [(V2DI "ISA_HAS_LSX") (V4DI "ISA_HAS_LASX")])
@@ -753,6 +824,39 @@ (define_expand "<simd_isa>_h<optab>w_q<u>_d<u>_punned"
DONE;
})
+(define_expand "<simd_isa>_maddw<ev_od>_q_d<u>_punned"
+ [(match_operand:DIVEC 0 "register_operand" "=f")
+ (match_operand:DIVEC 1 "register_operand" " 0")
+ (match_operand:DIVEC 2 "register_operand" " f")
+ (match_operand:DIVEC 3 "register_operand" " f")
+ (const_int zero_one)
+ (any_extend (const_int 0))]
+ ""
+{
+ rtx t = gen_reg_rtx (<WVEC_HALF>mode);
+ rtx op1 = gen_lowpart (<WVEC_HALF>mode, operands[1]);
+ emit_insn (gen_<simd_isa>_<x>vmaddw<ev_od>_q_d<u> (t, op1, operands[2],
+ operands[3]));
+ emit_move_insn (operands[0], gen_lowpart (<MODE>mode, t));
+ DONE;
+})
+
+(define_expand "<simd_isa>_maddw<ev_od>_q_du_d_punned"
+ [(match_operand:DIVEC 0 "register_operand" "=f")
+ (match_operand:DIVEC 1 "register_operand" " 0")
+ (match_operand:DIVEC 2 "register_operand" " f")
+ (match_operand:DIVEC 3 "register_operand" " f")
+ (const_int zero_one)]
+ ""
+{
+ rtx t = gen_reg_rtx (<WVEC_HALF>mode);
+ rtx op1 = gen_lowpart (<WVEC_HALF>mode, operands[1]);
+ emit_insn (gen_<simd_isa>_<x>vmaddw<ev_od>_q_du_d (t, op1, operands[2],
+ operands[3]));
+ emit_move_insn (operands[0], gen_lowpart (<MODE>mode, t));
+ DONE;
+})
+
; The LoongArch SX Instructions.
(include "lsx.md")
