I was looking at a regression on the bfin port with a recent change to
the IRA and stumbled across this just doing a general port healthyness
evaluation.
The ABS instruction in the blackfin ISA is defined as saturating on
INT_MIN, which is a bit unexpected. We certainly can't use it when
-fwrapv is enabled. Given the failures on the C23 uabs tests, I'm
inclined to just disable the pattern completely.
Fixes pr23047, uabs-2 and uabs-3.
While it's not a regression, it's the blackfin port, so I think we've
got a higher degree of freedom here.
Pushing to the trunk.
Jeff
commit 3e08a4ecea27c54fda90e8f58641b1986ad957e1
Author: Jeff Law <j...@ventanamicro.com>
Date: Wed Feb 5 14:22:33 2025 -0700
[committed] Disable ABS instruction on bfin port
I was looking at a regression on the bfin port with a recent change to the
IRA
and stumbled across this just doing a general port healthyness evaluation.
The ABS instruction in the blackfin ISA is defined as saturating on INT_MIN,
which is a bit unexpected. We certainly can't use it when -fwrapv is
enabled.
Given the failures on the C23 uabs tests, I'm inclined to just disable the
pattern completely.
Fixes pr23047, uabs-2 and uabs-3.
While it's not a regression, it's the blackfin port, so I think we've got a
higher degree of freedom here.
Pushing to the trunk.
gcc/
* config/bfin/bfin.md (abssi): Disable pattern.
diff --git a/gcc/config/bfin/bfin.md b/gcc/config/bfin/bfin.md
index 810bd52cadf..27c156b6c1e 100644
--- a/gcc/config/bfin/bfin.md
+++ b/gcc/config/bfin/bfin.md
@@ -1440,12 +1440,15 @@ (define_insn "sminsi3"
"%0 = min(%1,%2)%!"
[(set_attr "type" "dsp32")])
-(define_insn "abssi2"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (abs:SI (match_operand:SI 1 "register_operand" "d")))]
- ""
- "%0 = abs %1%!"
- [(set_attr "type" "dsp32")])
+;; The ABS instruction is defined as saturating. So at the least
+;; it is inappropriate for -fwrapv. This also fixes the C23 uabs
+;; tests.
+;;(define_insn "abssi2"
+;; [(set (match_operand:SI 0 "register_operand" "=d")
+;; (abs:SI (match_operand:SI 1 "register_operand" "d")))]
+;; ""
+;; "%0 = abs %1%!"
+;; [(set_attr "type" "dsp32")])
(define_insn "ssabssi2"
[(set (match_operand:SI 0 "register_operand" "=d")
