[PATCH] RISC-V: Fix ICE when prefetching addresses less than 12 bits for zicbop

[Jin Ma]

gcc/ChangeLog:

        * config/riscv/riscv.md: Change 'r' to 'p'.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/prefetch-zicbop-ice.c: New test.
---
 gcc/config/riscv/riscv.md                            | 2 +-
 gcc/testsuite/gcc.target/riscv/prefetch-zicbop-ice.c | 9 +++++++++
 2 files changed, 10 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/prefetch-zicbop-ice.c

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index c2a9de610526..86c39628ae8d 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -4370,7 +4370,7 @@ (define_insn "riscv_zero_<mode>"
 )
 
 (define_insn "prefetch"
-  [(prefetch (match_operand 0 "address_operand" "r")
+  [(prefetch (match_operand 0 "address_operand" "p")
              (match_operand 1 "imm5_operand" "i")
              (match_operand 2 "const_int_operand" "n"))]
   "TARGET_ZICBOP"
diff --git a/gcc/testsuite/gcc.target/riscv/prefetch-zicbop-ice.c 
b/gcc/testsuite/gcc.target/riscv/prefetch-zicbop-ice.c
new file mode 100644
index 000000000000..31908debb5cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/prefetch-zicbop-ice.c
@@ -0,0 +1,9 @@
+/* Test that we do not have ice when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zicbop -mabi=lp64d" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_zicbop -mabi=ilp32d" { target { rv32 } } } */
+
+void foo ()
+{
+  __builtin_prefetch ((int*)0xff, 1, 0);
+}
-- 
2.25.1