On 1/11/25 4:45 PM, Vineet Gupta wrote:
This seeming benign mistake caused a massive SPEC2017 Cactu regression
(2.1 trillion insn to 2.5 trillion) wiping out all the gains from my
recent sched1 improvement. Thankfully the issue was trivial to fix even
if hard to isolate.
On BPI3:
Before bug
----------
| Performance counter stats for './cactusBSSN_r_base-1':
|
| 4,557,471.02 msec task-clock:u # 1.000 CPUs
utilized
| 1,245 context-switches:u # 0.273 /sec
| 1 cpu-migrations:u # 0.000 /sec
| 205,376 page-faults:u # 45.064 /sec
| 7,291,944,801,307 cycles:u # 1.600 GHz
| 2,134,835,735,951 instructions:u # 0.29 insn per
cycle
| 10,799,296,738 branches:u # 2.370 M/sec
| 15,308,966 branch-misses:u # 0.14% of all
branches
|
| 4557.710508078 seconds time elapsed
Bug
---
| Performance counter stats for './cactusBSSN_r_base-2':
|
| 4,801,813.79 msec task-clock:u # 1.000 CPUs
utilized
| 8,066 context-switches:u # 1.680 /sec
| 1 cpu-migrations:u # 0.000 /sec
| 203,836 page-faults:u # 42.450 /sec
| 7,682,826,638,790 cycles:u # 1.600 GHz
| 2,503,133,291,344 instructions:u # 0.33 insn per
cycle
^^^^^^^^^^^^^^^^^
| 10,799,287,796 branches:u # 2.249 M/sec
| 16,641,200 branch-misses:u # 0.15% of all
branches
|
| 4802.616638386 seconds time elapsed
|
Fix
---
| Performance counter stats for './cactusBSSN_r_base-3':
|
| 4,556,170.75 msec task-clock:u # 1.000 CPUs
utilized
| 1,739 context-switches:u # 0.382 /sec
| 0 cpu-migrations:u # 0.000 /sec
| 203,458 page-faults:u # 44.655 /sec
| 7,289,854,613,923 cycles:u # 1.600 GHz
| 2,134,854,070,916 instructions:u # 0.29 insn per
cycle
| 10,799,296,807 branches:u # 2.370 M/sec
| 15,403,357 branch-misses:u # 0.14% of all
branches
|
| 4556.445490123 seconds time elapsed
Fixes: 46888571d242 "RISC-V: Add cr and cf constraint"
Signed-off-by: Vineet Gupta <vine...@rivosinc.com>
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_register_move_cost): Remove buggy
check.
OK
jeff
