Integer values and floating-point values need to be converted
by fmv series instructions. So if mode1 is MODE_INT and mode2
is MODE_FLOAT, we should return false in riscv_modes_tieable_p,
and vice versa.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_modes_tieable_p):
gcc/testsuite/ChangeLog:
* gcc.target/riscv/fwprop1-modes-tieable.c: New test.
---
gcc/config/riscv/riscv.cc | 5 ++
.../gcc.target/riscv/fwprop1-modes-tieable.c | 80 +++++++++++++++++++
2 files changed, 85 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/fwprop1-modes-tieable.c
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 65e09842fde..58b3b8c726c 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -9753,6 +9753,11 @@ riscv_modes_tieable_p (machine_mode mode1, machine_mode
mode2)
E.g. V2SI and DI are not tieable. */
if (riscv_v_ext_mode_p (mode1) != riscv_v_ext_mode_p (mode2))
return false;
+ if ((GET_MODE_CLASS (mode1) == MODE_FLOAT
+ && GET_MODE_CLASS (mode2) == MODE_INT)
+ || (GET_MODE_CLASS (mode2) == MODE_FLOAT
+ && GET_MODE_CLASS (mode1) == MODE_INT))
+ return false;
return (mode1 == mode2
|| !(GET_MODE_CLASS (mode1) == MODE_FLOAT
&& GET_MODE_CLASS (mode2) == MODE_FLOAT));
diff --git a/gcc/testsuite/gcc.target/riscv/fwprop1-modes-tieable.c
b/gcc/testsuite/gcc.target/riscv/fwprop1-modes-tieable.c
new file mode 100644
index 00000000000..05d775c31d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/fwprop1-modes-tieable.c
@@ -0,0 +1,80 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-rtl-fwprop1" } */
+/* { dg-skip-if "" { *-*-* } {"-Os" "-O1" "-O0" "-Og" "-Oz" "-flto"} } */
+/* { dg-final { scan-rtl-dump-not
"\\(and:DI^(\s|\n)?$\\(subreg:DI^(\s|\n)?$\\(reg/v:DF" "fwprop1" } } */
+
+#include <stdint.h>
+
+#define EXP_TABLE_BITS 7
+#define EXP_POLY_ORDER 5
+#define EXP2_POLY_ORDER 5
+struct exp_data
+{
+ double invln2N;
+ double shift;
+ double negln2hiN;
+ double negln2loN;
+ double poly[4]; /* Last four coefficients. */
+ double exp2_shift;
+ double exp2_poly[EXP2_POLY_ORDER];
+ uint64_t tab[2*(1 << EXP_TABLE_BITS)];
+};
+
+extern struct exp_data __exp_data;
+
+#define N (1 << EXP_TABLE_BITS)
+#define InvLn2N __exp_data.invln2N
+#define NegLn2hiN __exp_data.negln2hiN
+#define NegLn2loN __exp_data.negln2loN
+#define Shift __exp_data.shift
+#define T __exp_data.tab
+#define C2 __exp_data.poly[5 - EXP_POLY_ORDER]
+#define C3 __exp_data.poly[6 - EXP_POLY_ORDER]
+#define C4 __exp_data.poly[7 - EXP_POLY_ORDER]
+#define C5 __exp_data.poly[8 - EXP_POLY_ORDER]
+
+static inline uint64_t
+asuint64 (double f)
+{
+ union
+ {
+ double f;
+ uint64_t i;
+ } u = {f};
+ return u.i;
+}
+
+static inline double
+asdouble (uint64_t i)
+{
+ union
+ {
+ uint64_t i;
+ double f;
+ } u = {i};
+ return u.f;
+}
+
+double
+__testexp (double x)
+{
+ uint64_t ki, idx, sbits;
+ double kd, z, r, scale, tmp;
+
+ z = InvLn2N * x;
+
+ kd = z + Shift;
+ ki = asuint64 (kd);
+ kd -= Shift;
+
+ r = kd * NegLn2hiN + kd * NegLn2loN;
+
+ idx = (ki % N);
+
+ sbits = T[idx];
+
+ tmp = (r * C3);
+
+ scale = asdouble (sbits);
+ return scale * tmp;
+}
--
2.25.1
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