From: Pan Li <pan2...@intel.com>
Like the sat alu related testcase, the dump check of strided load/store
takes the rtl dump for the standard name MASK_LEN_STRIDED_LOAD for times.
But the rtl pass expand is somehow mutable by the middle-end change or
debug information.
After that we need to adjust the dump check time and again. This
patch would like to switch to tree optimized pass for the standard
name check, which is more stable up to a point.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f16.c: Take
tree-optimized pass for standard name check, and adjust the times.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f32.c: Ditto
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c: Ditto
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i16.c: Ditto
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i32.c: Ditto
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c: Ditto
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i8.c: Ditto
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u8.c: Ditto
Signed-off-by: Pan Li <pan2...@intel.com>
---
.../rvv/autovec/strided/strided_ld_st-1-f16.c | 10 +++++-----
.../rvv/autovec/strided/strided_ld_st-1-f32.c | 10 +++++-----
.../rvv/autovec/strided/strided_ld_st-1-f64.c | 10 +++++-----
.../rvv/autovec/strided/strided_ld_st-1-i16.c | 10 +++++-----
.../rvv/autovec/strided/strided_ld_st-1-i32.c | 18 +++++++++---------
.../rvv/autovec/strided/strided_ld_st-1-i64.c | 10 +++++-----
.../rvv/autovec/strided/strided_ld_st-1-i8.c | 10 +++++-----
.../rvv/autovec/strided/strided_ld_st-1-u16.c | 10 +++++-----
.../rvv/autovec/strided/strided_ld_st-1-u32.c | 18 +++++++++---------
.../rvv/autovec/strided/strided_ld_st-1-u64.c | 10 +++++-----
.../rvv/autovec/strided/strided_ld_st-1-u8.c | 10 +++++-----
11 files changed, 63 insertions(+), 63 deletions(-)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f16.c
index 4098774ba38..fb0d1d8a449 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f16.c
@@ -1,24 +1,24 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -mno-vector-strict-align
-fno-vect-cost-model -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -mno-vector-strict-align
-fno-vect-cost-model -fdump-tree-optimized" } */
#include "strided_ld_st.h"
DEF_STRIDED_LD_ST_FORM_1(_Float16)
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" {
target {
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "optimized" {
target {
any-opts "-O3"
no-opts "-mrvv-vector-bits=zvl"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" {
target {
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_STORE " 2 "optimized"
{ target {
any-opts "-O3"
no-opts "-mrvv-vector-bits=zvl"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" {
target {
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_LOAD " 1 "optimized" {
target {
any-opts "-O2"
no-opts "-mrvv-vector-bits=zvl"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" {
target {
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_STORE " 1 "optimized"
{ target {
any-opts "-O2"
no-opts "-mrvv-vector-bits=zvl"
} } } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f32.c
index e1d1063ec8c..48e0a096cf2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f32.c
@@ -1,24 +1,24 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -mno-vector-strict-align
-fno-vect-cost-model -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mno-vector-strict-align
-fno-vect-cost-model -fdump-tree-optimized" } */
#include "strided_ld_st.h"
DEF_STRIDED_LD_ST_FORM_1(float)
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" {
target {
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "optimized" {
target {
any-opts "-O3"
no-opts "-mrvv-vector-bits=zvl"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" {
target {
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_STORE " 2 "optimized"
{ target {
any-opts "-O3"
no-opts "-mrvv-vector-bits=zvl"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" {
target {
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_LOAD " 1 "optimized" {
target {
any-opts "-O2"
no-opts "-mrvv-vector-bits=zvl"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" {
target {
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_STORE " 1 "optimized"
{ target {
any-opts "-O2"
no-opts "-mrvv-vector-bits=zvl"
} } } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c
index 2be8854a0b6..c75365ef4fa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -mno-vector-strict-align
-fno-vect-cost-model -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mno-vector-strict-align
-fno-vect-cost-model -fdump-tree-optimized" } */
#include "strided_ld_st.h"
DEF_STRIDED_LD_ST_FORM_1(double)
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" {
target { any-opts "-O3" } } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" {
target { any-opts "-O3" } } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" {
target { any-opts "-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" {
target { any-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "optimized" {
target { any-opts "-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_STORE " 2 "optimized"
{ target { any-opts "-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_LOAD " 1 "optimized" {
target { any-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_STORE " 1 "optimized"
{ target { any-opts "-O2" } } } } */
/* { dg-final { scan-assembler-times {vlse64.v} 1 } } */
/* { dg-final { scan-assembler-times {vsse64.v} 1 { target { any-opts "-O2" }
} } } */
/* { dg-final { scan-assembler-times {vsse64.v} 2 { target { any-opts "-O3" }
} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i16.c
index 57b20a2f952..c70a5fb797f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i16.c
@@ -1,24 +1,24 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -mno-vector-strict-align
-fno-vect-cost-model -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mno-vector-strict-align
-fno-vect-cost-model -fdump-tree-optimized" } */
#include "strided_ld_st.h"
DEF_STRIDED_LD_ST_FORM_1(int16_t)
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" {
target {
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "optimized" {
target {
any-opts "-O3"
no-opts "-mrvv-vector-bits=zvl"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" {
target {
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_STORE " 2 "optimized"
{ target {
any-opts "-O3"
no-opts "-mrvv-vector-bits=zvl"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" {
target {
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_LOAD " 1 "optimized" {
target {
any-opts "-O2"
no-opts "-mrvv-vector-bits=zvl"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" {
target {
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_STORE " 1 "optimized"
{ target {
any-opts "-O2"
no-opts "-mrvv-vector-bits=zvl"
} } } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i32.c
index 1e4ae9fc98f..2a539d69d8a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i32.c
@@ -1,31 +1,31 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -mno-vector-strict-align
-fno-vect-cost-model -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mno-vector-strict-align
-fno-vect-cost-model -fdump-tree-optimized" } */
#include "strided_ld_st.h"
DEF_STRIDED_LD_ST_FORM_1(int32_t)
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" {
target {
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "optimized" {
target {
any-opts "-O3"
no-opts "-mrvv-vector-bits=zvl"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" {
target {
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_STORE " 2 "optimized"
{ target {
any-opts "-O3"
no-opts "-mrvv-vector-bits=zvl"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 8 "expand" {
target {
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_LOAD " 8 "optimized" {
target {
any-opts "-O3" "-mrvv-vector-bits=zvl"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 8 "expand" {
target {
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_STORE " 8 "optimized"
{ target {
any-opts "-O3" "-mrvv-vector-bits=zvl"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" {
target {
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_LOAD " 1 "optimized" {
target {
any-opts "-O2"
no-opts "-mrvv-vector-bits=zvl"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" {
target {
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_STORE " 1 "optimized"
{ target {
any-opts "-O2"
no-opts "-mrvv-vector-bits=zvl"
} } } } */
@@ -37,9 +37,9 @@ DEF_STRIDED_LD_ST_FORM_1(int32_t)
no-opts "-mrvv-vector-bits=zvl"
} } } } */
-/* { dg-final { scan-assembler-times {vlse32.v} 2 { target {
+/* { dg-final { scan-assembler-times {vlse32.v} 1 { target {
any-opts "-mrvv-vector-bits=zvl"
} } } } */
-/* { dg-final { scan-assembler-times {vsse32.v} 2 { target {
+/* { dg-final { scan-assembler-times {vsse32.v} 1 { target {
any-opts "-mrvv-vector-bits=zvl"
} } } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c
index 13003e2ccdc..35b894f1044 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -mno-vector-strict-align
-fno-vect-cost-model -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mno-vector-strict-align
-fno-vect-cost-model -fdump-tree-optimized" } */
#include "strided_ld_st.h"
DEF_STRIDED_LD_ST_FORM_1(int64_t)
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" {
target { any-opts "-O3" } } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" {
target { any-opts "-O3" } } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" {
target { any-opts "-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" {
target { any-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "optimized" {
target { any-opts "-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_STORE " 2 "optimized"
{ target { any-opts "-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_LOAD " 1 "optimized" {
target { any-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_STORE " 1 "optimized"
{ target { any-opts "-O2" } } } } */
/* { dg-final { scan-assembler-times {vlse64.v} 1 } } */
/* { dg-final { scan-assembler-times {vsse64.v} 1 { target { any-opts "-O2" }
} } } */
/* { dg-final { scan-assembler-times {vsse64.v} 2 { target { any-opts "-O3" }
} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i8.c
index d948f89abe7..098f078904d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i8.c
@@ -1,24 +1,24 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -mno-vector-strict-align
-fno-vect-cost-model -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mno-vector-strict-align
-fno-vect-cost-model -fdump-tree-optimized" } */
#include "strided_ld_st.h"
DEF_STRIDED_LD_ST_FORM_1(int8_t)
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" {
target {
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "optimized" {
target {
any-opts "-O3"
no-opts "-mrvv-vector-bits=zvl"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" {
target {
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_STORE " 2 "optimized"
{ target {
any-opts "-O3"
no-opts "-mrvv-vector-bits=zvl"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" {
target {
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_LOAD " 1 "optimized" {
target {
any-opts "-O2"
no-opts "-mrvv-vector-bits=zvl"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" {
target {
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_STORE " 1 "optimized"
{ target {
any-opts "-O2"
no-opts "-mrvv-vector-bits=zvl"
} } } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u16.c
index 78b6dbc1c49..8b00f99e63e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u16.c
@@ -1,24 +1,24 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -mno-vector-strict-align
-fno-vect-cost-model -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mno-vector-strict-align
-fno-vect-cost-model -fdump-tree-optimized" } */
#include "strided_ld_st.h"
DEF_STRIDED_LD_ST_FORM_1(uint16_t)
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" {
target {
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "optimized" {
target {
any-opts "-O3"
no-opts "-mrvv-vector-bits=zvl"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" {
target {
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_STORE " 2 "optimized"
{ target {
any-opts "-O3"
no-opts "-mrvv-vector-bits=zvl"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" {
target {
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_LOAD " 1 "optimized" {
target {
any-opts "-O2"
no-opts "-mrvv-vector-bits=zvl"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" {
target {
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_STORE " 1 "optimized"
{ target {
any-opts "-O2"
no-opts "-mrvv-vector-bits=zvl"
} } } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u32.c
index b1994d7d199..c116e74ca31 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u32.c
@@ -1,31 +1,31 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -mno-vector-strict-align
-fno-vect-cost-model -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mno-vector-strict-align
-fno-vect-cost-model -fdump-tree-optimized" } */
#include "strided_ld_st.h"
DEF_STRIDED_LD_ST_FORM_1(uint32_t)
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" {
target {
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "optimized" {
target {
any-opts "-O3"
no-opts "-mrvv-vector-bits=zvl"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" {
target {
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_STORE " 2 "optimized"
{ target {
any-opts "-O3"
no-opts "-mrvv-vector-bits=zvl"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 8 "expand" {
target {
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_LOAD " 8 "optimized" {
target {
any-opts "-O3" "-mrvv-vector-bits=zvl"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 8 "expand" {
target {
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_STORE " 8 "optimized"
{ target {
any-opts "-O3" "-mrvv-vector-bits=zvl"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" {
target {
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_LOAD " 1 "optimized" {
target {
any-opts "-O2"
no-opts "-mrvv-vector-bits=zvl"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" {
target {
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_STORE " 1 "optimized"
{ target {
any-opts "-O2"
no-opts "-mrvv-vector-bits=zvl"
} } } } */
@@ -37,9 +37,9 @@ DEF_STRIDED_LD_ST_FORM_1(uint32_t)
no-opts "-mrvv-vector-bits=zvl"
} } } } */
-/* { dg-final { scan-assembler-times {vlse32.v} 2 { target {
+/* { dg-final { scan-assembler-times {vlse32.v} 1 { target {
any-opts "-mrvv-vector-bits=zvl"
} } } } */
-/* { dg-final { scan-assembler-times {vsse32.v} 2 { target {
+/* { dg-final { scan-assembler-times {vsse32.v} 1 { target {
any-opts "-mrvv-vector-bits=zvl"
} } } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c
index 5df2caa793b..aa61544878d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -mno-vector-strict-align
-fno-vect-cost-model -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mno-vector-strict-align
-fno-vect-cost-model -fdump-tree-optimized" } */
#include "strided_ld_st.h"
DEF_STRIDED_LD_ST_FORM_1(uint64_t)
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" {
target { any-opts "-O3" } } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" {
target { any-opts "-O3" } } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" {
target { any-opts "-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" {
target { any-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "optimized" {
target { any-opts "-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_STORE " 2 "optimized"
{ target { any-opts "-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_LOAD " 1 "optimized" {
target { any-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_STORE " 1 "optimized"
{ target { any-opts "-O2" } } } } */
/* { dg-final { scan-assembler-times {vlse64.v} 1 } } */
/* { dg-final { scan-assembler-times {vsse64.v} 1 { target { any-opts "-O2" }
} } } */
/* { dg-final { scan-assembler-times {vsse64.v} 2 { target { any-opts "-O3" }
} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u8.c
index 7870ede903d..2d7338a7df8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u8.c
@@ -1,24 +1,24 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -mno-vector-strict-align
-fno-vect-cost-model -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mno-vector-strict-align
-fno-vect-cost-model -fdump-tree-optimized" } */
#include "strided_ld_st.h"
DEF_STRIDED_LD_ST_FORM_1(uint8_t)
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 4 "expand" {
target {
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "optimized" {
target {
any-opts "-O3"
no-opts "-mrvv-vector-bits=zvl"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 4 "expand" {
target {
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_STORE " 2 "optimized"
{ target {
any-opts "-O3"
no-opts "-mrvv-vector-bits=zvl"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" {
target {
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_LOAD " 1 "optimized" {
target {
any-opts "-O2"
no-opts "-mrvv-vector-bits=zvl"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" {
target {
+/* { dg-final { scan-tree-dump-times ".MASK_LEN_STRIDED_STORE " 1 "optimized"
{ target {
any-opts "-O2"
no-opts "-mrvv-vector-bits=zvl"
} } } } */
--
2.43.0
