From: Pan Li <pan2...@intel.com>
Almost the same as the RVV strided load, the vector strided store
doesn't involve the (mem:BLK (scratch)) to alias all other memories.
It will make the alias analysis only consider the base address of
strided store.
PR target/118075
gcc/ChangeLog:
* config/riscv/vector.md: Add the (mem:BLK (scratch)) as the
lhs of strided store define insn.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr118075-run-1.c: New test.
Signed-off-by: Pan Li <pan2...@intel.com>
---
gcc/config/riscv/vector.md | 19 +++++++--------
.../riscv/rvv/base/pr118075-run-1.c | 24 +++++++++++++++++++
2 files changed, 33 insertions(+), 10 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr118075-run-1.c
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 58406f3d17c..ff8f552b802 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -2396,18 +2396,17 @@ (define_insn "@pred_strided_load<mode>"
(set_attr "mode" "<MODE>")])
(define_insn "@pred_strided_store<mode>"
- [(set (match_operand:V_VLS 0 "memory_operand" "+m, m")
- (if_then_else:V_VLS
- (unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
- (match_operand 5 "const_int_operand" " i, i")
+ [(set (mem:BLK (scratch))
+ (unspec:BLK
+ [(match_operand:V_VLS 0 "memory_operand" " +m, m")
+ (unspec:<VM>
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 5 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (unspec:V_VLS
- [(match_operand 2 "<V_VLS:stride_predicate>"
"<V_VLS:stride_store_constraint>")
- (match_operand:V_VLS 3 "register_operand" " vr,
vr")] UNSPEC_STRIDED)
- (match_dup 0)))]
+ (match_operand 2 "<V_VLS:stride_predicate>"
"<V_VLS:stride_store_constraint>")
+ (match_operand:V_VLS 3 "register_operand" " vr, vr")]
UNSPEC_STRIDED))]
"TARGET_VECTOR"
"@
vsse<sew>.v\t%3,%0,%z2%p1
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr118075-run-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr118075-run-1.c
new file mode 100644
index 00000000000..120573a1e8c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr118075-run-1.c
@@ -0,0 +1,24 @@
+/* { dg-do run { target { riscv_v && rv64 } } } */
+/* { dg-additional-options "-std=c99 -O3 -march=rv64gcv_zvl256b
-mrvv-vector-bits=zvl" } */
+
+int a;
+int b[14];
+char c[14][14];
+
+int main() {
+ for (long f = 0; f < 14; ++f)
+ for (long g = 0; g < 4; ++g)
+ c[f][g] = 1;
+
+ for (short f = 0; f < 12; f += 1)
+ c[f][f] = b[f];
+
+ for (long f = 0; f < 4; ++f)
+ for (long g = 0; g < 14; ++g)
+ a ^= c[f][g];
+
+ if (a != 0)
+ __builtin_abort ();
+
+ return 0;
+}
--
2.43.0
