Some tests add options for V and Zvbb extensions, but do not have checks
whether the default abi supports them.
Fix by explicitly specifying ilp32d and lp64d ABI.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vandn-1.c: Specify ilp32d
ABI for RV32 targets, and lp64d for RV64 targets.
* gcc.target/riscv/rvv/autovec/binop/vrolr-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vwsll-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vwsll-template.h: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c:
Ditto.
* gcc.target/riscv/rvv/autovec/unop/clz-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/unop/ctz-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/unop/popcount-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/unop/popcount-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/unop/popcount-3.c: Ditto.
* gcc.target/riscv/rvv/base/cmpmem-1.c: Ditto.
* gcc.target/riscv/rvv/base/cmpmem-3.c: Ditto.
* gcc.target/riscv/rvv/base/cmpmem-4.c: Ditto.
* gcc.target/riscv/rvv/base/cpymem-1.c: Ditto.
* gcc.target/riscv/rvv/base/cpymem-2.c: Ditto.
* gcc.target/riscv/rvv/base/cpymem-3.c: Ditto.
* gcc.target/riscv/rvv/base/movmem-1.c: Ditto.
* gcc.target/riscv/rvv/base/pr115068.c: Ditto.
* gcc.target/riscv/rvv/base/setmem-1.c: Ditto.
* gcc.target/riscv/rvv/base/setmem-2.c: Ditto.
* gcc.target/riscv/rvv/base/setmem-3.c: Ditto.
* gcc.target/riscv/rvv/base/vwaddsub-1.c: Ditto.
Signed-off-by: Dimitar Dimitrov <dimi...@dinux.eu>
---
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vandn-1.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrolr-1.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-1.c | 2 ++
.../gcc.target/riscv/rvv/autovec/binop/vwsll-template.h | 2 ++
.../riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-1.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-1.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-3.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-3.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c | 2 ++
22 files changed, 44 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vandn-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vandn-1.c
index 3bb5bf8dd5b..bf7567b23e6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vandn-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vandn-1.c
@@ -2,6 +2,8 @@
/* { dg-add-options "riscv_v" } */
/* { dg-add-options "riscv_zvbb" } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */
+/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */
+/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */
#include "vandn-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrolr-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrolr-1.c
index 55dac27697c..841e2cebefa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrolr-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrolr-1.c
@@ -2,6 +2,8 @@
/* { dg-add-options "riscv_v" } */
/* { dg-add-options "riscv_zvbb" } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */
+/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */
+/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */
#include "vrolr-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-1.c
index a2e5b4f5aa1..1af3c37b3ab 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-1.c
@@ -2,6 +2,8 @@
/* { dg-add-options "riscv_v" } */
/* { dg-add-options "riscv_zvbb" } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */
+/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */
+/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */
#include "vwsll-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-template.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-template.h
index 376cbaee0d5..a9f35a54fe0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-template.h
@@ -2,6 +2,8 @@
/* { dg-add-options "riscv_v" } */
/* { dg-add-options "riscv_zvbb" } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */
+/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */
+/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */
#include <stdint-gcc.h>
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c
index 1fd3644886a..5f98688f916 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c
@@ -2,6 +2,8 @@
/* { dg-add-options "riscv_v" } */
/* { dg-add-options "riscv_zvbb" } */
/* { dg-additional-options "-fno-vect-cost-model -fdump-tree-vect-details
-mrvv-max-lmul=m4" } */
+/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */
+/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-1.c
index c27d9d399b9..c03decc5228 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-1.c
@@ -2,6 +2,8 @@
/* { dg-add-options "riscv_v" } */
/* { dg-add-options "riscv_zvbb" } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */
+/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */
+/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */
#include "clz-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-1.c
index d5989bd5aad..caf4175492a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-1.c
@@ -2,6 +2,8 @@
/* { dg-add-options "riscv_v" } */
/* { dg-add-options "riscv_zvbb" } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */
+/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */
+/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */
#include "ctz-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c
index 1396e46ec8c..28e369d8acc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c
@@ -1,6 +1,8 @@
/* { dg-do compile } */
/* { dg-add-options "riscv_v" } */
/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model
-fdump-tree-vect-details" } */
+/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */
+/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c
index 116cc304da3..d2cbeaf594b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c
@@ -1,6 +1,8 @@
/* { dg-do compile } */
/* { dg-add-options "riscv_v" } */
/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model
-fdump-tree-slp-details" } */
+/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */
+/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */
int x[8];
int y[8];
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-3.c
index 00b87a07fd8..7e261e49d80 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-3.c
@@ -2,6 +2,8 @@
/* { dg-add-options "riscv_v" } */
/* { dg-add-options "riscv_zvbb" } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */
+/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */
+/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */
#include "popcount-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c
index 6bc8b07bc2c..2a3dc84c912 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c
@@ -1,6 +1,8 @@
/* { dg-do compile } */
/* { dg-add-options riscv_v } */
/* { dg-additional-options "-O3 -mrvv-max-lmul=dynamic" } */
+/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */
+/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */
/* { dg-final { check-function-bodies "**" "" } } */
#define MIN_VECTOR_BYTES (__riscv_v_min_vlen / 8)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c
index 5ca31af90fb..1d17a5083d4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c
@@ -1,6 +1,8 @@
/* { dg-do compile } */
/* { dg-add-options riscv_v } */
/* { dg-additional-options "-O3 -mrvv-max-lmul=m1" } */
+/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */
+/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */
/* { dg-final { check-function-bodies "**" "" } } */
#define MIN_VECTOR_BYTES (__riscv_v_min_vlen / 8)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c
index 5860b27a233..d3f8210c0b1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c
@@ -1,6 +1,8 @@
/* { dg-do compile } */
/* { dg-add-options riscv_v } */
/* { dg-additional-options "-O3 -mrvv-max-lmul=m8" } */
+/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */
+/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */
/* { dg-final { check-function-bodies "**" "" } } */
#define MIN_VECTOR_BYTES (__riscv_v_min_vlen / 8)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
index 81d14d83633..867211056f6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
@@ -1,6 +1,8 @@
/* { dg-do compile } */
/* { dg-additional-options "-O1 -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-add-options riscv_v } */
+/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */
+/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */
/* { dg-final { check-function-bodies "**" "" } } */
#if 0 /* Using include files when using a multilib-relevant -march option is
dicey */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c
index 7b6a429f34c..98cc21493f6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c
@@ -1,6 +1,8 @@
/* { dg-do compile } */
/* { dg-additional-options "-O1 -fno-schedule-insns -fno-schedule-insns2
-mrvv-max-lmul=m8" } */
/* { dg-add-options riscv_v } */
+/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */
+/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */
/* { dg-final { check-function-bodies "**" "" } } */
typedef struct { char c[16]; } c16;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-3.c
index f07078ba6a7..4be97c3f2bf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-3.c
@@ -1,6 +1,8 @@
/* { dg-do compile } */
/* { dg-additional-options "-O1 -fno-schedule-insns -fno-schedule-insns2
-mrvv-max-lmul=m8" } */
/* { dg-add-options riscv_v } */
+/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */
+/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */
/* { dg-final { check-function-bodies "**" "" } } */
#define MIN_VECTOR_BYTES (__riscv_v_min_vlen / 8)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c
index 1f148bc7052..926aa0b1ebe 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c
@@ -1,6 +1,8 @@
/* { dg-do compile } */
/* { dg-add-options riscv_v } */
/* { dg-additional-options "-O3 -mrvv-max-lmul=dynamic" } */
+/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */
+/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */
/* { dg-final { check-function-bodies "**" "" } } */
#define MIN_VECTOR_BYTES (__riscv_v_min_vlen / 8)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c
index 8359e81629d..4d63ef5c916 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c
@@ -1,6 +1,8 @@
/* { dg-do compile } */
/* { dg-add-options riscv_v } */
/* { dg-additional-options "-std=gnu99" } */
+/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */
+/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */
#include <stdint.h>
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c
index 22844ff348c..f5b6a3417d4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c
@@ -1,6 +1,8 @@
/* { dg-do compile } */
/* { dg-add-options riscv_v } */
/* { dg-additional-options "-O3 -mrvv-max-lmul=dynamic" } */
+/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */
+/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */
/* { dg-final { check-function-bodies "**" "" } } */
#define MIN_VECTOR_BYTES (__riscv_v_min_vlen / 8)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c
index 838fbebadff..8304d723c78 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c
@@ -1,6 +1,8 @@
/* { dg-do compile } */
/* { dg-add-options riscv_v } */
/* { dg-additional-options "-O3 -mrvv-max-lmul=m1" } */
+/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */
+/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */
/* { dg-final { check-function-bodies "**" "" } } */
#define MIN_VECTOR_BYTES (__riscv_v_min_vlen / 8)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c
index 44933819715..ec1114e12af 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c
@@ -1,6 +1,8 @@
/* { dg-do compile } */
/* { dg-add-options riscv_v } */
/* { dg-additional-options "-O3 -mrvv-max-lmul=m8" } */
+/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */
+/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */
/* { dg-final { check-function-bodies "**" "" } } */
#define MIN_VECTOR_BYTES (__riscv_v_min_vlen / 8)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c
index 196215a1f7b..9a85f069d85 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c
@@ -1,6 +1,8 @@
/* { dg-do compile } */
/* { dg-add-options riscv_v } */
/* { dg-additional-options "-std=gnu99 -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */
+/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */
#include <stdint.h>
#include <riscv_vector.h>
--
2.47.1
