On Mon, 18 Nov 2024, Maciej W. Rozycki wrote: > As it happens these data races also apply to BWX Alpha systems, as I have > discovered in the course of this effort, although owing to how the Alpha > backend of GCC has implemented block copy and clear operations rather than > actual hardware limitations, for example GCC will happily produce code > such as: > > ldbu $1,0($3) > stw $31,8($3) > stq $1,0($3) > > to zero a 9-byte member at the byte offset of 1 of a quadword-aligned > struct, happily clobbering a 1-byte member at the beginning of said struct > if there is a concurrent or parallel write to that member in the middle of > the unprotected RMW sequence.
Ping for: <https://inbox.sourceware.org/gcc-patches/[email protected]/> <https://inbox.sourceware.org/gcc-patches/[email protected]/> (this will presumably need tweaks similar to ones made to __builtin_memcpy tests, to exclude for AVR targets and to mark as expensive) <https://inbox.sourceware.org/gcc-patches/[email protected]/> <https://inbox.sourceware.org/gcc-patches/[email protected]/> <https://inbox.sourceware.org/gcc-patches/[email protected]/> <https://inbox.sourceware.org/gcc-patches/[email protected]/> <https://inbox.sourceware.org/gcc-patches/[email protected]/> <https://inbox.sourceware.org/gcc-patches/[email protected]/> <https://inbox.sourceware.org/gcc-patches/[email protected]/> <https://inbox.sourceware.org/gcc-patches/[email protected]/> <https://inbox.sourceware.org/gcc-patches/[email protected]/> <https://inbox.sourceware.org/gcc-patches/[email protected]/> <https://inbox.sourceware.org/gcc-patches/[email protected]/> Maciej
