Oh, I saw the second patch is just adding testcase, I think all comments are minor, so no need v2, I will address those minor change and commit after verified on my hand :)
On Thu, Nov 28, 2024 at 2:52 PM Kito Cheng <kito.ch...@gmail.com> wrote: > > I incline to just keep sifive-vector, it although actually an IME > (Integrated Matrix Extension), but we don't have too much > instructions, also we will have more SiFive vector extension which not > IME, so I think just put in sifive-vector is fine. > > And this patch is generally in good shape, I assume we just need one > more version :) > > On Thu, Nov 28, 2024 at 10:39 AM <shiyul...@iscas.ac.cn> wrote: > > > > From: yulong <shiyul...@iscas.ac.cn> > > > > This commit adds intrinsics support for Xsfvqmaccqoq/dod. > > > > Co-Authored by: Kito Cheng <kito.ch...@sifive.com> > > Co-Authored by: Monk Chiang <monk.chi...@sifive.com> > > Drop me and Monk, we aren't really involved in the development, so > just keeping PLCT folks is fine. > > > diff --git a/gcc/config/riscv/sifive-vector.md > > b/gcc/config/riscv/sifive-vector.md > > new file mode 100644 > > index 00000000000..373e4d6dd86 > > --- /dev/null > > +++ b/gcc/config/riscv/sifive-vector.md > > @@ -0,0 +1,179 @@ > > Following comment plz remove. > > > +;; Keep this list and the one above riscv_print_operand in sync. > > +;; The special asm out single letter directives following a '%' are: > > +;; h -- Print the high-part relocation associated with OP, after stripping > > +;; any outermost HIGH. > > +;; R -- Print the low-part relocation associated with OP. > > +;; C -- Print the integer branch condition for comparison OP. > > +;; A -- Print the atomic operation suffix for memory model OP. > > +;; F -- Print a FENCE if the memory model requires a release. > > +;; z -- Print x0 if OP is zero, otherwise print OP normally. > > +;; i -- Print i if the operand is not a register. > > +;; S -- Print shift-index of single-bit mask OP. > > +;; T -- Print shift-index of inverted single-bit mask OP. > > +;; ~ -- Print w if TARGET_64BIT is true; otherwise not print anything. > > Until here. > > > > diff --git a/gcc/config/riscv/vector-iterators.md > > b/gcc/config/riscv/vector-iterators.md > > index 92cb651ce49..850fac1ba22 100644 > > --- a/gcc/config/riscv/vector-iterators.md > > +++ b/gcc/config/riscv/vector-iterators.md > > @@ -103,6 +103,7 @@ > > UNSPEC_WREDUC_SUM_ORDERED > > UNSPEC_WREDUC_SUM_UNORDERED > > UNSPEC_SELECT_MASK > > + > > ^ drop this unnecessary blankline
