> The DejaGnu routine "riscv_get_arch" fails to infer the correct > architecture string when GCC is built for RV32EC. This causes invalid > architecture string to be produced by "add_options_for_riscv_v": > xgcc: error: '-march=rv32cv': first ISA subset must be 'e', 'i' or 'g' > > Fix by adding the E base ISA variant to the list of possible architecture > modifiers. > > Also, the V extension is added to the machine string without checking > whether dependent extensions are available. This results in errors when > GCC is built for RV32EC: > Executing on host: .../xgcc ... -march=rv32ecv ... > cc1: error: ILP32E ABI does not support the 'D' extension > cc1: sorry, unimplemented: Currently the 'V' implementation requires the > 'M' extension > > Fix by disabling vector tests for RISC-V if V extension cannot be added > to current architecture. > > Tested riscv32-none-elf for -march=rv32ec using GNU simulator. Most of > the remaining failures are due to explicit addition of vector options, > yet missing "dg-require-effective-target riscv_v_ok":
LGTM. Thanks. -- Regards Robin
