There are separate patterns for predicated FADD, FSUB, and FMUL. Previously they each had their own in-built split to convert the instruction to unpredicated form where appropriate. However, it's more convenient for later patches if we use a single separate split instead.
gcc/ * config/aarch64/iterators.md (SVE_COND_FP): New code attribute. * config/aarch64/aarch64-sve.md: Use a single define_split to handle the conversion of predicated FADD, FSUB, and FMUL into unpredicated forms. --- gcc/config/aarch64/aarch64-sve.md | 47 ++++++++++++++----------------- gcc/config/aarch64/iterators.md | 6 ++++ 2 files changed, 27 insertions(+), 26 deletions(-) diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index affdb24a93d..1602668271e 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -5272,9 +5272,25 @@ (define_insn_and_rewrite "*cond_<optab><mode>_any_strict" ;; - FSUB ;; ------------------------------------------------------------------------- +;; Split a predicated instruction whose predicate is unused into an +;; unpredicated instruction. +(define_split + [(set (match_operand:SVE_FULL_F 0 "register_operand") + (unspec:SVE_FULL_F + [(match_operand:<VPRED> 1 "register_operand") + (match_operand:SI 4 "aarch64_sve_gp_strictness") + (match_operand:SVE_FULL_F 2 "register_operand") + (match_operand:SVE_FULL_F 3 "register_operand")] + <SVE_COND_FP>))] + "TARGET_SVE + && reload_completed + && INTVAL (operands[4]) == SVE_RELAXED_GP" + [(set (match_dup 0) + (SVE_UNPRED_FP_BINARY:SVE_FULL_F (match_dup 2) (match_dup 3)))] +) + ;; Unpredicated floating-point binary operations (post-RA only). -;; These are generated by splitting a predicated instruction whose -;; predicate is unused. +;; These are generated by the split above. (define_insn "*post_ra_<sve_fp_op><mode>3" [(set (match_operand:SVE_FULL_F 0 "register_operand" "=w") (SVE_UNPRED_FP_BINARY:SVE_FULL_F @@ -5640,7 +5656,7 @@ (define_insn_and_rewrite "*cond_<optab><mode>_any_const_strict" ;; ------------------------------------------------------------------------- ;; Predicated floating-point addition. -(define_insn_and_split "@aarch64_pred_<optab><mode>" +(define_insn "@aarch64_pred_<optab><mode>" [(set (match_operand:SVE_FULL_F 0 "register_operand") (unspec:SVE_FULL_F [(match_operand:<VPRED> 1 "register_operand") @@ -5658,13 +5674,6 @@ (define_insn_and_split "@aarch64_pred_<optab><mode>" [ ?&w , Upl , w , vsN , i ; yes ] movprfx\t%0, %2\;fsub\t%0.<Vetype>, %1/m, %0.<Vetype>, #%N3 [ ?&w , Upl , w , w , Ui1 ; yes ] movprfx\t%0, %2\;fadd\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype> } - ; Split the unpredicated form after reload, so that we don't have - ; the unnecessary PTRUE. - "&& reload_completed - && register_operand (operands[3], <MODE>mode) - && INTVAL (operands[4]) == SVE_RELAXED_GP" - [(set (match_dup 0) (plus:SVE_FULL_F (match_dup 2) (match_dup 3)))] - "" ) ;; Predicated floating-point addition of a constant, merging with the @@ -5963,7 +5972,7 @@ (define_insn_and_rewrite "*cond_<optab><mode>_any_strict" ;; ------------------------------------------------------------------------- ;; Predicated floating-point subtraction. -(define_insn_and_split "@aarch64_pred_<optab><mode>" +(define_insn "@aarch64_pred_<optab><mode>" [(set (match_operand:SVE_FULL_F 0 "register_operand") (unspec:SVE_FULL_F [(match_operand:<VPRED> 1 "register_operand") @@ -5980,13 +5989,6 @@ (define_insn_and_split "@aarch64_pred_<optab><mode>" [ ?&w , Upl , vsA , w , i ; yes ] movprfx\t%0, %3\;fsubr\t%0.<Vetype>, %1/m, %0.<Vetype>, #%2 [ ?&w , Upl , w , w , Ui1 ; yes ] movprfx\t%0, %2\;fsub\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype> } - ; Split the unpredicated form after reload, so that we don't have - ; the unnecessary PTRUE. - "&& reload_completed - && register_operand (operands[2], <MODE>mode) - && INTVAL (operands[4]) == SVE_RELAXED_GP" - [(set (match_dup 0) (minus:SVE_FULL_F (match_dup 2) (match_dup 3)))] - "" ) ;; Predicated floating-point subtraction from a constant, merging with the @@ -6392,7 +6394,7 @@ (define_insn_and_rewrite "*aarch64_cond_abd<mode>_any_strict" ;; ------------------------------------------------------------------------- ;; Predicated floating-point multiplication. -(define_insn_and_split "@aarch64_pred_<optab><mode>" +(define_insn "@aarch64_pred_<optab><mode>" [(set (match_operand:SVE_FULL_F 0 "register_operand") (unspec:SVE_FULL_F [(match_operand:<VPRED> 1 "register_operand") @@ -6408,13 +6410,6 @@ (define_insn_and_split "@aarch64_pred_<optab><mode>" [ ?&w , Upl , w , vsM , i ; yes ] movprfx\t%0, %2\;fmul\t%0.<Vetype>, %1/m, %0.<Vetype>, #%3 [ ?&w , Upl , w , w , Ui1 ; yes ] movprfx\t%0, %2\;fmul\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype> } - ; Split the unpredicated form after reload, so that we don't have - ; the unnecessary PTRUE. - "&& reload_completed - && register_operand (operands[3], <MODE>mode) - && INTVAL (operands[4]) == SVE_RELAXED_GP" - [(set (match_dup 0) (mult:SVE_FULL_F (match_dup 2) (match_dup 3)))] - "" ) ;; Merging forms are handled through SVE_COND_FP_BINARY and diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 147cc95c269..0ce88758a57 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -2971,6 +2971,12 @@ (define_code_attr sve_pred_int_rhs2_operand (define_code_attr inc_dec [(minus "dec") (ss_minus "sqdec") (us_minus "uqdec") (plus "inc") (ss_plus "sqinc") (us_plus "uqinc")]) +;; The predicated FP operation associated with each rtl code. This is only +;; useful for operations that have both predicated and unpredicated forms. +(define_code_attr SVE_COND_FP [(plus "UNSPEC_COND_FADD") + (minus "UNSPEC_COND_FSUB") + (mult "UNSPEC_COND_FMUL")]) + ;; ------------------------------------------------------------------- ;; Int Iterators. ;; ------------------------------------------------------------------- -- 2.25.1