Hello,
This patch series is a revised version of the following:
https://gcc.gnu.org/pipermail/gcc-patches/2024-November/668229.html.
In this version:
- Patch 09/12 has been updated with comments provided by Matevos, which
were missing in the previously submitted series.
- Patch 06/12 includes the following change made by Richard Sandiford,
which is necessary for the code to compile and hasn't been added to the GCC
master branch.
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -4312,7 +4312,7 @@
;; RTL uses GCC vector extension indices throughout so flip only for
assembly.
;; Extracting lane zero is split into a simple move when it is between SIMD
;; registers or a store.
-(define_insn_and_split "aarch64_get_lane<mode>"
+(define_insn_and_split "@aarch64_get_lane<mode>"
[(set (match_operand:<VEL> 0 "aarch64_simd_nonimmediate_operand" "=?r, w,
Utv")
(vec_select:<VEL>
(match_operand:VALL_F16 1 "register_operand" "w, w, w")
Thanks,
Mariam
