On Tue, Oct 22, 2024 at 2:34 PM Haochen Jiang <haochen.ji...@intel.com> wrote:
>
> From: "Hu, Lin1" <lin1...@intel.com>
>
> gcc/ChangeLog:
>
> * common/config/i386/cpuinfo.h (get_available_features): Detect movrs.
> * common/config/i386/i386-common.cc
> (OPTION_MASK_ISA2_MOVRS_SET): New.
> (OPTION_MASK_ISA2_MOVRS_UNSET): Ditto.
> (ix86_handle_option): Handle -mmovrs.
> * common/config/i386/i386-cpuinfo.h
> (enum processor_features): Add FEATURE_MOVRS.
> * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for movrs.
> * config.gcc: Add movrsintrin.h
> * config/i386/cpuid.h (bit_MOVRS): New.
> * config/i386/i386-builtin-types.def:
> Add DEF_FUNCTION_TYPE (CHAR, PCCHAR), (SHORT, PCSHORT), (INT, PCINT),
> (INT64, PCINT64).
> * config/i386/i386-builtin.def (BDESC): Add new builtins.
> * config/i386/i386-c.cc (ix86_target_macros_internal):
> * config/i386/i386-expand.cc (ix86_expand_special_args_builtin):
> Define
> __MOVRS__.
> * config/i386/i386-isa.def (MOVRS): Add DEF_PTA(MOVRS)
> * config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p):
> Handle movrs.
> * config/i386/i386.md (movrs<mode>): New.
> diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
> index 3f5a58d6167..8e41afb7638 100644
> --- a/gcc/config/i386/i386.md
> +++ b/gcc/config/i386/i386.md
> @@ -367,6 +367,9 @@
> ;; For AMX-TILE
> UNSPECV_LDTILECFG
> UNSPECV_STTILECFG
> +
> + ;; For MOVRS support
> + UNSPECV_MOVRS
> ])
>
> ;; Constants to represent rounding modes in the ROUND instruction
> @@ -28567,19 +28570,21 @@
> [(prefetch (match_operand 0 "address_operand")
> (match_operand:SI 1 "const_int_operand")
> (match_operand:SI 2 "const_int_operand"))]
> - "TARGET_3DNOW || TARGET_PREFETCH_SSE || TARGET_PRFCHW"
> + "TARGET_3DNOW || TARGET_PREFETCH_SSE || TARGET_PRFCHW
> + || TARGET_MOVRS"
> {
> - bool write = operands[1] != const0_rtx;
> + int write = INTVAL (operands[1]);
> int locality = INTVAL (operands[2]);
>
> gcc_assert (IN_RANGE (locality, 0, 3));
> + gcc_assert (IN_RANGE (write, 0, 2));
>
> /* Use 3dNOW prefetch in case we are asking for write prefetch not
> supported by SSE counterpart (non-SSE2 athlon machines) or the
> SSE prefetch is not available (K6 machines). Otherwise use SSE
> prefetch as it allows specifying of locality. */
>
> - if (write)
> + if (write == 1)
> {
> if (TARGET_PRFCHW)
> operands[2] = GEN_INT (3);
> @@ -28587,11 +28592,24 @@
> operands[2] = GEN_INT (3);
> else if (TARGET_PREFETCH_SSE)
> operands[1] = const0_rtx;
> - else
> + else if (write == 0)
> {
> gcc_assert (TARGET_3DNOW);
> operands[2] = GEN_INT (3);
> }
> + else
> + {
> + if (TARGET_MOVRS)
> + ;
> + else if (TARGET_PREFETCH_SSE)
> + operands[1] = const0_rtx;
> + else
> + {
> + gcc_assert (TARGET_3DNOW);
> + operands[1] = const0_rtx;
> + operands[2] = GEN_INT (3);
> + }
> + }
These changes aren't mentioned in ChangeLog and they caused:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117416
H.J.
