Signed-off-by: Torbjörn SVENSSON <torbjorn.svens...@foss.st.com>
---
.../arm/cmse/mainline/8_1m/hard-sp/cmse-5.c | 15 ++-
.../arm/cmse/mainline/8_1m/hard/cmse-5.c | 15 ++-
.../arm/cmse/mainline/8_1m/soft/cmse-5.c | 16 +++-
.../arm/cmse/mainline/8_1m/softfp-sp/cmse-5.c | 17 ++--
.../arm/cmse/mainline/8_1m/softfp/cmse-5.c | 16 ++--
.../arm/cmse/mainline/8m/hard-sp/cmse-5.c | 91 ++++++++++++-------
.../arm/cmse/mainline/8m/hard/cmse-5.c | 71 ++++++++++-----
.../arm/cmse/mainline/8m/soft/cmse-5.c | 22 +++--
.../arm/cmse/mainline/8m/softfp-sp/cmse-5.c | 90 +++++++++++-------
.../arm/cmse/mainline/8m/softfp/cmse-5.c | 66 +++++++++-----
10 files changed, 274 insertions(+), 145 deletions(-)
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-5.c
b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-5.c
index dc62b742ba5..58fd8884422 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-5.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-5.c
@@ -2,11 +2,16 @@
/* { dg-options "-mcmse -mfloat-abi=hard -mfpu=fpv5-sp-d16" } */
/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } {
"-mfloat-abi=hard" } } */
/* { dg-skip-if "Skip these if testing double precision" {*-*-*} {"-mfpu=fpv[4-5]-d16"}
{""} } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
#include "../../../cmse-5.x"
-/* { dg-final { scan-assembler "vstr\tFPCXTNS, \\\[sp, #-4\\\]!" } } */
-/* { dg-final { scan-assembler "vscclrm\t\{s1-s15, VPR\}" } } */
-/* { dg-final { scan-assembler "clrm\t\{r0, r1, r2, r3, ip, APSR\}" } } */
-/* { dg-final { scan-assembler "vldr\tFPCXTNS, \\\[sp\\\], #4" } } */
-/* { dg-final { scan-assembler "bxns" } } */
+/*
+** __acle_se_foo:
+** vstr FPCXTNS, \[sp, #-4\]!
+** ...
+** vscclrm \{s1-s15, VPR\}
+** clrm \{r0, r1, r2, r3, ip, APSR\}
+** vldr FPCXTNS, \[sp\], #4
+** bxns lr
+*/
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard/cmse-5.c
b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard/cmse-5.c
index 55e7a4f7ae0..44ed6fbb8ed 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard/cmse-5.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard/cmse-5.c
@@ -2,11 +2,16 @@
/* { dg-options "-mcmse -mfloat-abi=hard -mfpu=fpv5-d16" } */
/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } {
"-mfloat-abi=hard" } } */
/* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"}
{""} } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
#include "../../../cmse-5.x"
-/* { dg-final { scan-assembler "vstr\tFPCXTNS, \\\[sp, #-4\\\]!" } } */
-/* { dg-final { scan-assembler "vscclrm\t\{s1-s15, VPR\}" } } */
-/* { dg-final { scan-assembler "clrm\t\{r0, r1, r2, r3, ip, APSR\}" } } */
-/* { dg-final { scan-assembler "vldr\tFPCXTNS, \\\[sp\\\], #4" } } */
-/* { dg-final { scan-assembler "bxns" } } */
+/*
+** __acle_se_foo:
+** vstr FPCXTNS, \[sp, #-4\]!
+** ...
+** vscclrm \{s1-s15, VPR\}
+** clrm \{r0, r1, r2, r3, ip, APSR\}
+** vldr FPCXTNS, \[sp\], #4
+** bxns lr
+*/
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-5.c
b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-5.c
index d3a3a742b8b..5bb55e2489f 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-5.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-5.c
@@ -1,13 +1,19 @@
/* { dg-do compile } */
/* { dg-options "-mcmse -mfloat-abi=soft" } */
/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } {
"-mfloat-abi=soft" } } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
#include "../../../cmse-5.x"
-/* { dg-final { scan-assembler "vstr\tFPCXTNS, \\\[sp, #-4\\\]!" } } */
+/*
+** __acle_se_foo:
+** vstr FPCXTNS, \[sp, #-4\]!
+** ...
+** vscclrm \{s0-s15, VPR\}
+** clrm \{r1, r2, r3, ip, APSR\}
+** vldr FPCXTNS, \[sp\], #4
+** bxns lr
+*/
+
/* { dg-final { scan-assembler-not "vmov" } } */
/* { dg-final { scan-assembler-not "vmsr" } } */
-/* { dg-final { scan-assembler "vscclrm\t\{s0-s15, VPR\}" } } */
-/* { dg-final { scan-assembler "clrm\t\{r1, r2, r3, ip, APSR\}" } } */
-/* { dg-final { scan-assembler "vldr\tFPCXTNS, \\\[sp\\\], #4" } } */
-/* { dg-final { scan-assembler "bxns" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-5.c
b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-5.c
index bbe16cee9c2..55f067d46c0 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-5.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-5.c
@@ -2,13 +2,18 @@
/* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-sp-d16" } */
/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } {
"-mfloat-abi=softfp" } } */
/* { dg-skip-if "Skip these if testing double precision" {*-*-*} {"-mfpu=fpv[4-5]-d16"}
{""} } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
#include "../../../cmse-5.x"
-/* { dg-final { scan-assembler "__acle_se_foo:" } } */
-/* { dg-final { scan-assembler "vstr\tFPCXTNS, \\\[sp, #-4\\\]!" } } */
+/*
+** __acle_se_foo:
+** vstr FPCXTNS, \[sp, #-4\]!
+** ...
+** vscclrm \{s0-s15, VPR\}
+** clrm \{r1, r2, r3, ip, APSR\}
+** vldr FPCXTNS, \[sp\], #4
+** bxns lr
+*/
+
/* { dg-final { scan-assembler-not "mov\tr0, lr" } } */
-/* { dg-final { scan-assembler "vscclrm\t\{s0-s15, VPR\}" } } */
-/* { dg-final { scan-assembler "clrm\t\{r1, r2, r3, ip, APSR\}" } } */
-/* { dg-final { scan-assembler "vldr\tFPCXTNS, \\\[sp\\\], #4" } } */
-/* { dg-final { scan-assembler "bxns" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-5.c
b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-5.c
index c7dda6a3d60..97881de43b2 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-5.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-5.c
@@ -2,12 +2,16 @@
/* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-d16" } */
/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } {
"-mfloat-abi=softfp" } } */
/* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"}
{""} } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
#include "../../../cmse-5.x"
-/* { dg-final { scan-assembler "__acle_se_foo:" } } */
-/* { dg-final { scan-assembler "vstr\tFPCXTNS, \\\[sp, #-4\\\]!" } } */
-/* { dg-final { scan-assembler "vscclrm\t\{s0-s15, VPR\}" } } */
-/* { dg-final { scan-assembler "clrm\t\{r1, r2, r3, ip, APSR\}" } } */
-/* { dg-final { scan-assembler "vldr\tFPCXTNS, \\\[sp\\\], #4" } } */
-/* { dg-final { scan-assembler "bxns" } } */
+/*
+** __acle_se_foo:
+** vstr FPCXTNS, \[sp, #-4\]!
+** ...
+** vscclrm \{s0-s15, VPR\}
+** clrm \{r1, r2, r3, ip, APSR\}
+** vldr FPCXTNS, \[sp\], #4
+** bxns lr
+*/
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/hard-sp/cmse-5.c
b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/hard-sp/cmse-5.c
index 3b73c0ee2fb..bf635a8863c 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/hard-sp/cmse-5.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/hard-sp/cmse-5.c
@@ -2,37 +2,66 @@
/* { dg-options "-mcmse -mfloat-abi=hard -mfpu=fpv5-sp-d16" } */
/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } {
"-mfloat-abi=hard" } } */
/* { dg-skip-if "Skip these if testing double precision" {*-*-*} {"-mfpu=fpv[4-5]-d16"}
{""} } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
#include "../../../cmse-5.x"
-/* { dg-final { scan-assembler "mov\tr0, lr" } } */
-/* { dg-final { scan-assembler "mov\tr1, lr" } } */
-/* { dg-final { scan-assembler "mov\tr2, lr" } } */
-/* { dg-final { scan-assembler "mov\tr3, lr" } } */
-/* { dg-final { scan-assembler-not "vmov\.f32\ts0, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f32\ts1, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f32\ts2, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f32\ts3, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f32\ts4, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f32\ts5, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f32\ts6, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f32\ts7, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f32\ts8, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f32\ts9, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f32\ts10, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f32\ts11, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f32\ts12, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f32\ts13, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f32\ts14, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f32\ts15, #1\.0" } } */
-/* { dg-final { scan-assembler "msr\tAPSR_nzcvq, lr" { target { ! arm_dsp } }
} } */
-/* { dg-final { scan-assembler "msr\tAPSR_nzcvqg, lr" { target arm_dsp } } } */
-/* { dg-final { scan-assembler "push\t{r4}" } } */
-/* { dg-final { scan-assembler "vmrs\tip, fpscr" } } */
-/* { dg-final { scan-assembler "movw\tr4, #65376" } } */
-/* { dg-final { scan-assembler "movt\tr4, #4095" } } */
-/* { dg-final { scan-assembler "and\tip, r4" } } */
-/* { dg-final { scan-assembler "vmsr\tfpscr, ip" } } */
-/* { dg-final { scan-assembler "pop\t{r4}" } } */
-/* { dg-final { scan-assembler "mov\tip, lr" } } */
-/* { dg-final { scan-assembler "bxns" } } */
+/*
+** __acle_se_foo:
+**...
+** (
+** mov r0, lr
+** mov r1, lr
+** mov r2, lr
+** mov r3, lr
+** ...
+** vmov.f32 s1, #1\.0e\+0
+** vmov.f32 s2, #1\.0e\+0
+** vmov.f32 s3, #1\.0e\+0
+** vmov.f32 s4, #1\.0e\+0
+** vmov.f32 s5, #1\.0e\+0
+** vmov.f32 s6, #1\.0e\+0
+** vmov.f32 s7, #1\.0e\+0
+** vmov.f32 s8, #1\.0e\+0
+** vmov.f32 s9, #1\.0e\+0
+** vmov.f32 s10, #1\.0e\+0
+** vmov.f32 s11, #1\.0e\+0
+** vmov.f32 s12, #1\.0e\+0
+** vmov.f32 s13, #1\.0e\+0
+** vmov.f32 s14, #1\.0e\+0
+** vmov.f32 s15, #1\.0e\+0
+** |
+** vmov.f32 s1, #1\.0e\+0
+** vmov.f32 s2, #1\.0e\+0
+** vmov.f32 s3, #1\.0e\+0
+** vmov.f32 s4, #1\.0e\+0
+** vmov.f32 s5, #1\.0e\+0
+** vmov.f32 s6, #1\.0e\+0
+** vmov.f32 s7, #1\.0e\+0
+** vmov.f32 s8, #1\.0e\+0
+** vmov.f32 s9, #1\.0e\+0
+** vmov.f32 s10, #1\.0e\+0
+** vmov.f32 s11, #1\.0e\+0
+** vmov.f32 s12, #1\.0e\+0
+** vmov.f32 s13, #1\.0e\+0
+** vmov.f32 s14, #1\.0e\+0
+** vmov.f32 s15, #1\.0e\+0
+** ...
+** mov r0, lr
+** mov r1, lr
+** mov r2, lr
+** mov r3, lr
+** )
+** msr APSR_nzcvqg?, lr
+** push (\{r4\})
+** vmrs ip, fpscr
+** movw r4, #65376
+** movt r4, #4095
+** and ip, r4
+** vmsr fpscr, ip
+** pop \1
+** mov ip, lr
+** bxns lr
+*/
+
+/* { dg-final { scan-assembler-not "vmov\.f32\ts0, #1\.0e\+0" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/hard/cmse-5.c
b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/hard/cmse-5.c
index d6e758cc98e..d8ac7c961cc 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/hard/cmse-5.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/hard/cmse-5.c
@@ -2,30 +2,53 @@
/* { dg-options "-mcmse -mfloat-abi=hard -mfpu=fpv5-d16" } */
/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } {
"-mfloat-abi=hard" } } */
/* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"}
{""} } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
#include "../../../cmse-5.x"
-/* { dg-final { scan-assembler "mov\tr0, lr" } } */
-/* { dg-final { scan-assembler "mov\tr1, lr" } } */
-/* { dg-final { scan-assembler "mov\tr2, lr" } } */
-/* { dg-final { scan-assembler "mov\tr3, lr" } } */
-/* { dg-final { scan-assembler-not "vmov\.f32\ts0, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f32\ts1, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f64\td1, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f64\td2, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f64\td3, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f64\td4, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f64\td5, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f64\td6, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f64\td7, #1\.0" } } */
-/* { dg-final { scan-assembler "msr\tAPSR_nzcvq, lr" { target { ! arm_dsp } }
} } */
-/* { dg-final { scan-assembler "msr\tAPSR_nzcvqg, lr" { target arm_dsp } } } */
-/* { dg-final { scan-assembler "push\t{r4}" } } */
-/* { dg-final { scan-assembler "vmrs\tip, fpscr" } } */
-/* { dg-final { scan-assembler "movw\tr4, #65376" } } */
-/* { dg-final { scan-assembler "movt\tr4, #4095" } } */
-/* { dg-final { scan-assembler "and\tip, r4" } } */
-/* { dg-final { scan-assembler "vmsr\tfpscr, ip" } } */
-/* { dg-final { scan-assembler "pop\t{r4}" } } */
-/* { dg-final { scan-assembler "mov\tip, lr" } } */
-/* { dg-final { scan-assembler "bxns" } } */
+/*
+** __acle_se_foo:
+** ...
+** (
+** mov r0, lr
+** mov r1, lr
+** mov r2, lr
+** mov r3, lr
+** ...
+** vmov.f32 s1, #1\.0e\+0
+** vmov.f64 d1, #1\.0e\+0
+** vmov.f64 d2, #1\.0e\+0
+** vmov.f64 d3, #1\.0e\+0
+** vmov.f64 d4, #1\.0e\+0
+** vmov.f64 d5, #1\.0e\+0
+** vmov.f64 d6, #1\.0e\+0
+** vmov.f64 d7, #1\.0e\+0
+** |
+** vmov.f32 s1, #1\.0e\+0
+** vmov.f64 d1, #1\.0e\+0
+** vmov.f64 d2, #1\.0e\+0
+** vmov.f64 d3, #1\.0e\+0
+** vmov.f64 d4, #1\.0e\+0
+** vmov.f64 d5, #1\.0e\+0
+** vmov.f64 d6, #1\.0e\+0
+** vmov.f64 d7, #1\.0e\+0
+** ...
+** mov r0, lr
+** mov r1, lr
+** mov r2, lr
+** mov r3, lr
+** )
+** msr APSR_nzcvqg?, lr
+** push (\{r4\})
+** vmrs ip, fpscr
+** movw r4, #65376
+** movt r4, #4095
+** and ip, r4
+** vmsr fpscr, ip
+** pop \1
+** mov ip, lr
+** bxns lr
+*/
+
+/* { dg-final { scan-assembler-not "vmov\.f64\td0, #1\.0e\+0" } } */
+/* { dg-final { scan-assembler-not "vmov\.f32\ts0, #1\.0e\+0" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/soft/cmse-5.c
b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/soft/cmse-5.c
index 71971b094c0..9a28d555b04 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/soft/cmse-5.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/soft/cmse-5.c
@@ -1,15 +1,19 @@
/* { dg-do compile } */
/* { dg-options "-mcmse -mfloat-abi=soft" } */
/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } {
"-mfloat-abi=soft" } } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
#include "../../../cmse-5.x"
-/* { dg-final { scan-assembler "mov\tr1, lr" } } */
-/* { dg-final { scan-assembler "mov\tr2, lr" } } */
-/* { dg-final { scan-assembler "mov\tr3, lr" } } */
-/* { dg-final { scan-assembler "mov\tip, lr" } } */
-/* { dg-final { scan-assembler-not "vmov" } } */
-/* { dg-final { scan-assembler-not "vmsr" } } */
-/* { dg-final { scan-assembler "msr\tAPSR_nzcvq, lr" { target { ! arm_dsp } }
} } */
-/* { dg-final { scan-assembler "msr\tAPSR_nzcvqg, lr" { target arm_dsp } } } */
-/* { dg-final { scan-assembler "bxns" } } */
+/*
+** __acle_se_foo:
+**...
+** mov r1, lr
+** mov r2, lr
+** mov r3, lr
+** mov ip, lr
+** msr APSR_nzcvqg?, lr
+** bxns lr
+*/
+
+/* { dg-final { scan-assembler-not "mov\tr0, lr" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/softfp-sp/cmse-5.c
b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/softfp-sp/cmse-5.c
index f550b77f616..881d17f720c 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/softfp-sp/cmse-5.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/softfp-sp/cmse-5.c
@@ -2,38 +2,66 @@
/* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-sp-d16" } */
/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } {
"-mfloat-abi=softfp" } } */
/* { dg-skip-if "Skip these if testing double precision" {*-*-*} {"-mfpu=fpv[4-5]-d16"}
{""} } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
#include "../../../cmse-5.x"
-/* { dg-final { scan-assembler "__acle_se_foo:" } } */
+/*
+** __acle_se_foo:
+** ...
+** (
+** mov r1, lr
+** mov r2, lr
+** mov r3, lr
+** ...
+** vmov.f32 s0, #1\.0e\+0
+** vmov.f32 s1, #1\.0e\+0
+** vmov.f32 s2, #1\.0e\+0
+** vmov.f32 s3, #1\.0e\+0
+** vmov.f32 s4, #1\.0e\+0
+** vmov.f32 s5, #1\.0e\+0
+** vmov.f32 s6, #1\.0e\+0
+** vmov.f32 s7, #1\.0e\+0
+** vmov.f32 s8, #1\.0e\+0
+** vmov.f32 s9, #1\.0e\+0
+** vmov.f32 s10, #1\.0e\+0
+** vmov.f32 s11, #1\.0e\+0
+** vmov.f32 s12, #1\.0e\+0
+** vmov.f32 s13, #1\.0e\+0
+** vmov.f32 s14, #1\.0e\+0
+** vmov.f32 s15, #1\.0e\+0
+** |
+** vmov.f32 s0, #1\.0e\+0
+** vmov.f32 s1, #1\.0e\+0
+** vmov.f32 s2, #1\.0e\+0
+** vmov.f32 s3, #1\.0e\+0
+** vmov.f32 s4, #1\.0e\+0
+** vmov.f32 s5, #1\.0e\+0
+** vmov.f32 s6, #1\.0e\+0
+** vmov.f32 s7, #1\.0e\+0
+** vmov.f32 s8, #1\.0e\+0
+** vmov.f32 s9, #1\.0e\+0
+** vmov.f32 s10, #1\.0e\+0
+** vmov.f32 s11, #1\.0e\+0
+** vmov.f32 s12, #1\.0e\+0
+** vmov.f32 s13, #1\.0e\+0
+** vmov.f32 s14, #1\.0e\+0
+** vmov.f32 s15, #1\.0e\+0
+** ...
+** mov r1, lr
+** mov r2, lr
+** mov r3, lr
+** )
+** msr APSR_nzcvqg?, lr
+** push (\{r4\})
+** vmrs ip, fpscr
+** movw r4, #65376
+** movt r4, #4095
+** and ip, r4
+** vmsr fpscr, ip
+** pop \1
+** mov ip, lr
+** bxns lr
+*/
+
/* { dg-final { scan-assembler-not "mov\tr0, lr" } } */
-/* { dg-final { scan-assembler "mov\tr1, lr" } } */
-/* { dg-final { scan-assembler "mov\tr2, lr" } } */
-/* { dg-final { scan-assembler "mov\tr3, lr" } } */
-/* { dg-final { scan-assembler "vmov\.f32\ts0, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f32\ts1, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f32\ts2, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f32\ts3, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f32\ts4, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f32\ts5, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f32\ts6, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f32\ts7, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f32\ts8, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f32\ts9, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f32\ts10, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f32\ts11, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f32\ts12, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f32\ts13, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f32\ts14, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f32\ts15, #1\.0" } } */
-/* { dg-final { scan-assembler "msr\tAPSR_nzcvq, lr" { target { ! arm_dsp } }
} } */
-/* { dg-final { scan-assembler "msr\tAPSR_nzcvqg, lr" { target arm_dsp } } } */
-/* { dg-final { scan-assembler "push\t{r4}" } } */
-/* { dg-final { scan-assembler "vmrs\tip, fpscr" } } */
-/* { dg-final { scan-assembler "movw\tr4, #65376" } } */
-/* { dg-final { scan-assembler "movt\tr4, #4095" } } */
-/* { dg-final { scan-assembler "and\tip, r4" } } */
-/* { dg-final { scan-assembler "vmsr\tfpscr, ip" } } */
-/* { dg-final { scan-assembler "pop\t{r4}" } } */
-/* { dg-final { scan-assembler "mov\tip, lr" } } */
-/* { dg-final { scan-assembler "bxns" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/softfp/cmse-5.c
b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/softfp/cmse-5.c
index cf8f3ab135a..5167a7babb3 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/softfp/cmse-5.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/softfp/cmse-5.c
@@ -2,30 +2,50 @@
/* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-d16" } */
/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } {
"-mfloat-abi=softfp" } } */
/* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"}
{""} } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
#include "../../../cmse-5.x"
-/* { dg-final { scan-assembler "__acle_se_foo:" } } */
+/*
+** __acle_se_foo:
+**...
+** (
+** vmov.f64 d0, #1\.0e\+0
+** vmov.f64 d1, #1\.0e\+0
+** vmov.f64 d2, #1\.0e\+0
+** vmov.f64 d3, #1\.0e\+0
+** vmov.f64 d4, #1\.0e\+0
+** vmov.f64 d5, #1\.0e\+0
+** vmov.f64 d6, #1\.0e\+0
+** vmov.f64 d7, #1\.0e\+0
+** ...
+** mov r1, lr
+** mov r2, lr
+** mov r3, lr
+** |
+** mov r1, lr
+** mov r2, lr
+** mov r3, lr
+** ...
+** vmov.f64 d0, #1\.0e\+0
+** vmov.f64 d1, #1\.0e\+0
+** vmov.f64 d2, #1\.0e\+0
+** vmov.f64 d3, #1\.0e\+0
+** vmov.f64 d4, #1\.0e\+0
+** vmov.f64 d5, #1\.0e\+0
+** vmov.f64 d6, #1\.0e\+0
+** vmov.f64 d7, #1\.0e\+0
+** )
+** msr APSR_nzcvqg?, lr
+** push \{r4\}
+** vmrs ip, fpscr
+** movw r4, #65376
+** movt r4, #4095
+** and ip, r4
+** vmsr fpscr, ip
+** pop \{r4\}
+** mov ip, lr
+** bxns lr
+*/
+
/* { dg-final { scan-assembler-not "mov\tr0, lr" } } */
-/* { dg-final { scan-assembler "mov\tr1, lr" } } */
-/* { dg-final { scan-assembler "mov\tr2, lr" } } */
-/* { dg-final { scan-assembler "mov\tr3, lr" } } */
-/* { dg-final { scan-assembler "vmov\.f64\td0, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f64\td1, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f64\td2, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f64\td3, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f64\td4, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f64\td5, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f64\td6, #1\.0" } } */
-/* { dg-final { scan-assembler "vmov\.f64\td7, #1\.0" } } */
-/* { dg-final { scan-assembler "msr\tAPSR_nzcvq, lr" { target { ! arm_dsp } }
} } */
-/* { dg-final { scan-assembler "msr\tAPSR_nzcvqg, lr" { target arm_dsp } } } */
-/* { dg-final { scan-assembler "push\t{r4}" } } */
-/* { dg-final { scan-assembler "vmrs\tip, fpscr" } } */
-/* { dg-final { scan-assembler "movw\tr4, #65376" } } */
-/* { dg-final { scan-assembler "movt\tr4, #4095" } } */
-/* { dg-final { scan-assembler "and\tip, r4" } } */
-/* { dg-final { scan-assembler "vmsr\tfpscr, ip" } } */
-/* { dg-final { scan-assembler "pop\t{r4}" } } */
-/* { dg-final { scan-assembler "mov\tip, lr" } } */
-/* { dg-final { scan-assembler "bxns" } } */
