Tested on hppa64-hp-hpux11.11 and hppa-unknown-linux-gnu. Committed to trunk.
Dave
---
hppa: Use stack slot SP-40 to copy between integer and floating-point registers
2024-10-06 John David Anglin <dang...@gcc.gnu.org>
gcc/ChangeLog:
* config/pa/pa-64.h (PA_SECONDARY_MEMORY_NEEDED): Define
to false. Update comment.
* config/pa/pa.md: Modify 64-bit move patterns to support
copying between integer and floating-point registers using
stack slot SP-40.
diff --git a/gcc/config/pa/pa-64.h b/gcc/config/pa/pa-64.h
index b676468d2ce..3fae3f851e5 100644
--- a/gcc/config/pa/pa-64.h
+++ b/gcc/config/pa/pa-64.h
@@ -91,9 +91,9 @@ along with GCC; see the file COPYING3. If not see
the RTL to avoid scheduling related problems. For example, the
store and load could be separated by a call to a pure or const
function which has no frame and this function might also use SP-16.
- We have 14-bit immediates on the 64-bit port, so we use secondary
- memory for the copies. */
-#define PA_SECONDARY_MEMORY_NEEDED(MODE, CLASS1, CLASS2) \
- (MAYBE_FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2) \
- || MAYBE_FP_REG_CLASS_P (CLASS2) != FP_REG_CLASS_P (CLASS1))
-
+
+ On the 64-bit port, I couldn't get SECONDARY_MEMORY_NEEDED to work
+ with LRA, so I modified the move patterns to use SP-40. The HP
+ compiler also uses this slot in the frame marker for moving data
+ between the general and floating-point registers. */
+#define PA_SECONDARY_MEMORY_NEEDED(MODE, CLASS1, CLASS2) false
diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index f0520bb2c35..bf59b7f601e 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -2222,9 +2222,9 @@
(define_insn ""
[(set (match_operand:SI 0 "move_dest_operand"
- "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
+ "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T,?r,?*f")
(match_operand:SI 1 "move_src_operand"
- "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
+ "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f,*f,r"))]
"(register_operand (operands[0], SImode)
|| reg_or_0_operand (operands[1], SImode))
&& !TARGET_SOFT_FLOAT
@@ -2241,10 +2241,12 @@
{mfctl|mfctl,w} %%sar,%0
fcpy,sgl %f1,%0
fldw%F1 %1,%0
- fstw%F0 %1,%0"
- [(set_attr "type"
"load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
+ fstw%F0 %1,%0
+ fstw %1,-40(%%sp)\n\tldw -40(%%sp),%0
+ stw %1,-40(%%sp)\n\tfldw -40(%%sp),%0"
+ [(set_attr "type"
"load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore,fpstore_load,store_fpload")
(set_attr "pa_combine_type" "addmove")
- (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
+ (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,8,8")])
(define_insn ""
[(set (match_operand:SI 0 "move_dest_operand"
@@ -4107,9 +4109,9 @@
(define_insn ""
[(set (match_operand:DF 0 "move_dest_operand"
- "=!*r,*r,*r,*r,*r,Q,f,f,T")
+ "=!*r,*r,*r,*r,*r,Q,f,f,T,?*r,?f")
(match_operand:DF 1 "move_src_operand"
- "!*rG,J,N,K,RQ,*rG,fG,RT,f"))]
+ "!*rG,J,N,K,RQ,*rG,fG,RT,f,f,*r"))]
"(register_operand (operands[0], DFmode)
|| reg_or_0_operand (operands[1], DFmode))
&& !TARGET_SOFT_FLOAT && TARGET_64BIT"
@@ -4122,10 +4124,12 @@
std%M0 %r1,%0
fcpy,dbl %f1,%0
fldd%F1 %1,%0
- fstd%F0 %1,%0"
- [(set_attr "type" "move,move,move,shift,load,store,fpalu,fpload,fpstore")
+ fstd%F0 %1,%0
+ fstd %1,-40(%%sp)\n\tldd -40(%%sp),%0
+ std %1,-40(%%sp)\n\tfldd -40(%%sp),%0"
+ [(set_attr "type"
"move,move,move,shift,load,store,fpalu,fpload,fpstore,fpstore_load,store_fpload")
(set_attr "pa_combine_type" "addmove")
- (set_attr "length" "4,4,4,4,4,4,4,4,4")])
+ (set_attr "length" "4,4,4,4,4,4,4,4,4,8,8")])
(define_insn ""
[(set (match_operand:DF 0 "move_dest_operand"
@@ -4281,9 +4285,9 @@
(define_insn ""
[(set (match_operand:DI 0 "move_dest_operand"
- "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
+ "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T,?r,?*f")
(match_operand:DI 1 "move_src_operand"
- "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
+ "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f,*f,r"))]
"(register_operand (operands[0], DImode)
|| reg_or_0_operand (operands[1], DImode))
&& !TARGET_SOFT_FLOAT && TARGET_64BIT"
@@ -4299,10 +4303,12 @@
{mfctl|mfctl,w} %%sar,%0
fcpy,dbl %f1,%0
fldd%F1 %1,%0
- fstd%F0 %1,%0"
- [(set_attr "type"
"load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
+ fstd%F0 %1,%0
+ fstd %1,-40(%%sp)\n\tldd -40(%%sp),%0
+ std %1,-40(%%sp)\n\tfldd -40(%%sp),%0"
+ [(set_attr "type"
"load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore,fpstore_load,store_fpload")
(set_attr "pa_combine_type" "addmove")
- (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
+ (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,8,8")])
(define_insn ""
[(set (match_operand:DI 0 "move_dest_operand"
@@ -4513,9 +4519,9 @@
(define_insn ""
[(set (match_operand:SF 0 "move_dest_operand"
- "=f,!*r,f,*r,T,Q")
+ "=f,!*r,f,*r,T,Q,?*r,?f")
(match_operand:SF 1 "reg_or_0_or_mem_operand"
- "fG,!*rG,RT,RQ,f,*rG"))]
+ "fG,!*rG,RT,RQ,f,*rG,f,*r"))]
"(register_operand (operands[0], SFmode)
|| reg_or_0_operand (operands[1], SFmode))
&& !TARGET_SOFT_FLOAT
@@ -4526,10 +4532,12 @@
fldw%F1 %1,%0
ldw%M1 %1,%0
fstw%F0 %1,%0
- stw%M0 %r1,%0"
- [(set_attr "type" "fpalu,move,fpload,load,fpstore,store")
+ stw%M0 %r1,%0
+ fstw %1,-40(%%sp)\n\tldw -40(%%sp),%0
+ stw %1,-40(%%sp)\n\tfldw -40(%%sp),%0"
+ [(set_attr "type"
"fpalu,move,fpload,load,fpstore,store,fpstore_load,store_fpload")
(set_attr "pa_combine_type" "addmove")
- (set_attr "length" "4,4,4,4,4,4")])
+ (set_attr "length" "4,4,4,4,4,4,8,8")])
(define_insn ""
[(set (match_operand:SF 0 "move_dest_operand"
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