On 9/5/24 11:07 PM, Zhao Dingyi wrote:
This patch aims to add the missing instruction types to the XiangShan-
Nanhu scheduler model.
The current XiangShan -Nanhu model lacks the trap, atomic trap,
fcvt_i2f, and fcvt_f2i instructions.
The trap, atomic, and i2f instructions belong to xs_jmp_rs. [1]
The f2i instruction belongs to xs_fmisc_rs.[2]
[1] https://github.com/OpenXiangShan/XiangShan/blob/v2.0/src/main/scala/
xiangshan/package.scala#L780 <https://github.com/OpenXiangShan/
XiangShan/blob/v2.0/src/main/scala/xiangshan/package.scala#L780>
[2] https://github.com/OpenXiangShan/XiangShan/blob/v2.0/src/main/scala/
xiangshan/backend/decode/DecodeUnit.scala#L290 <https://github.com/
OpenXiangShan/XiangShan/blob/v2.0/src/main/scala/xiangshan/backend/
decode/DecodeUnit.scala#L290>
gcc/ChangeLog: * config/riscv/xiangshan.md: Add atomic, trap,
fcvt_i2f, fcvt_f2i.
Thanks. I wasn't able to apply the patch directory as it appears your
mailer inserted a bunch of additional whitespace. No worries though,
it's simple enough to just recreate.
I suspect there's other missing cases in the xiangshan.md file, but this
clearly doesn't make anything worse and should avoid at least some of
the assertions we've seen when tuning for this chip.
Pushed to the trunk.
Thanks again,
jeff
