On Wed, Jun 6, 2012 at 12:19 PM, Edmar <ed...@freescale.com> wrote: > On 06/06/2012 08:57 AM, David Edelsohn wrote: >> >> On Tue, Jun 5, 2012 at 4:21 PM, Edmar<ed...@freescale.com> wrote: >>> >>> David, Michael, >>> >>> Here is the new type "popcnt" patch that I had separated from previous >>> E5500/E6500 submission, also added the changes suggested by Michael >>> Meissner (detailed bellow). >>> I am missing some details for power6. (Could not find any documentation) >>> >>> Bootstrapped with no regressions, all languages enabled, configured >>> for target powerpc64 and used "--with-cpu=<>" for each of power6, power7, >>> and 970. >>> All work performed on svn revison number 188200.
2012-06-05 Edmar Wienskoski <ed...@freescale.com> * config/rs6000/rs6000.md (define_attr "type"): New type popcnt. (popcntb<mode>2): Add attribute type popcnt. (popcntd<mode>2): Ditto. * config/rs6000/power4.md (define_insn_reservation): Add type popcnt. * config/rs6000/power5.md (define_insn_reservation): Ditto. * config/rs6000/power7.md (define_insn_reservation): Ditto. * config/rs6000/476.md (define_insn_reservation): Ditto. * config/rs6000/power6.md (define_insn_reservation): New reservation for popcnt instructions. Sorry, I thought that the patch added an additional target flags. The patch to add a "popcnt" instruction attribute is okay and a 1 cycle latency for POWER processors is fine. Thanks, David
