On Thu, Jun 27, 2024 at 9:23 AM Hu, Lin1 <lin1...@intel.com> wrote:
>
> Hi, all
>
> This patch aims to refactor vcvttps2qq/vcvtqq2ps patterns for remove redundant
> round_*_modev8sf_condition.
>
> Bootstrapped and regtested on x86-64-linux-gnu, OK for trunk?
Ok.
>
> BRs,
> Lin
>
> gcc/ChangeLog:
>
> * config/i386/sse.md
>
> (float<floatunssuffix><sselongvecmodelower><mode>2<mask_name><round_name>):
> Refactor the pattern.
>
> (unspec_fix<vcvtt_uns_suffix>_trunc<mode><sselongvecmodelower>2<mask_name><round_saeonly_name>):
> Ditto.
>
> (fix<fixunssuffix>_trunc<mode><sselongvecmodelower>2<mask_name><round_saeonly_name>):
> Ditto.
> * config/i386/subst.md (round_modev8sf_condition): Remove.
> (round_saeonly_modev8sf_condition): Ditto.
> ---
> gcc/config/i386/sse.md | 51 +++++++++++++++++-----------------------
> gcc/config/i386/subst.md | 2 --
> 2 files changed, 22 insertions(+), 31 deletions(-)
>
> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> index 0be2dcd8891..cf8de6347cf 100644
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -1157,6 +1157,9 @@ (define_mode_attr ssePSmodelower
> (define_mode_attr ssePSmode2
> [(V8DI "V8SF") (V4DI "V4SF")])
>
> +(define_mode_attr ssePSmode2lower
> + [(V8DI "v8sf") (V4DI "v4sf")])
> +
> ;; Mapping of vector modes back to the scalar modes
> (define_mode_attr ssescalarmode
> [(V64QI "QI") (V32QI "QI") (V16QI "QI")
> @@ -8861,27 +8864,17 @@ (define_insn
> "float<floatunssuffix><sseintvecmodelower><mode>2<mask_name><round_
>
> ;; For float<floatunssuffix><sselondveclower><mode> insn patterns
> (define_mode_attr qq2pssuff
> - [(V8SF "") (V4SF "{y}")])
> -
> -(define_mode_attr sselongvecmode
> - [(V8SF "V8DI") (V4SF "V4DI")])
> -
> -(define_mode_attr sselongvecmodelower
> - [(V8SF "v8di") (V4SF "v4di")])
> -
> -(define_mode_attr sseintvecmode3
> - [(V8SF "XI") (V4SF "OI")
> - (V8DF "OI") (V4DF "TI")])
> + [(V8DI "") (V4DI "{y}")])
>
> -(define_insn
> "float<floatunssuffix><sselongvecmodelower><mode>2<mask_name><round_name>"
> - [(set (match_operand:VF1_128_256VL 0 "register_operand" "=v")
> - (any_float:VF1_128_256VL
> - (match_operand:<sselongvecmode> 1 "nonimmediate_operand"
> "<round_constraint>")))]
> - "TARGET_AVX512DQ && <round_modev8sf_condition>"
> +(define_insn
> "float<floatunssuffix><mode><ssePSmode2lower>2<mask_name><round_name>"
> + [(set (match_operand:<ssePSmode2> 0 "register_operand" "=v")
> + (any_float:<ssePSmode2>
> + (match_operand:VI8_256_512 1 "nonimmediate_operand"
> "<round_constraint>")))]
> + "TARGET_AVX512DQ && <round_mode512bit_condition>"
> "vcvt<floatsuffix>qq2ps<qq2pssuff>\t{<round_mask_op2>%1,
> %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
> [(set_attr "type" "ssecvt")
> (set_attr "prefix" "evex")
> - (set_attr "mode" "<MODE>")])
> + (set_attr "mode" "<sseinsnmode>")])
>
> (define_expand "avx512dq_float<floatunssuffix>v2div2sf2"
> [(set (match_operand:V4SF 0 "register_operand" "=v")
> @@ -9416,26 +9409,26 @@ (define_insn
> "fixuns_notrunc<mode><sseintvecmodelower>2<mask_name><round_name>"
> (set_attr "prefix" "evex")
> (set_attr "mode" "<sseintvecmode2>")])
>
> -(define_insn
> "unspec_fix<vcvtt_uns_suffix>_trunc<mode><sselongvecmodelower>2<mask_name><round_saeonly_name>"
> - [(set (match_operand:<sselongvecmode> 0 "register_operand" "=v")
> - (unspec:<sselongvecmode>
> - [(match_operand:VF1_128_256VL 1 "<round_saeonly_nimm_predicate>"
> "<round_saeonly_constraint>")]
> +(define_insn
> "unspec_fix<vcvtt_uns_suffix>_trunc<ssePSmode2lower><mode>2<mask_name><round_saeonly_name>"
> + [(set (match_operand:VI8_256_512 0 "register_operand" "=v")
> + (unspec:VI8_256_512
> + [(match_operand:<ssePSmode2> 1 "<round_saeonly_nimm_predicate>"
> "<round_saeonly_constraint>")]
> UNSPEC_VCVTT_U))]
> - "TARGET_AVX512DQ && <round_saeonly_modev8sf_condition>"
> + "TARGET_AVX512DQ && <round_saeonly_mode512bit_condition>"
> "vcvttps2<vcvtt_suffix>qq\t{<round_saeonly_mask_op2>%1,
> %0<mask_operand2>|%0<mask_operand2>, %1<round_saeonly_mask_op2>}"
> [(set_attr "type" "ssecvt")
> (set_attr "prefix" "evex")
> - (set_attr "mode" "<sseintvecmode3>")])
> + (set_attr "mode" "<sseinsnmode>")])
>
> -(define_insn
> "fix<fixunssuffix>_trunc<mode><sselongvecmodelower>2<mask_name><round_saeonly_name>"
> - [(set (match_operand:<sselongvecmode> 0 "register_operand" "=v")
> - (any_fix:<sselongvecmode>
> - (match_operand:VF1_128_256VL 1 "<round_saeonly_nimm_predicate>"
> "<round_saeonly_constraint>")))]
> - "TARGET_AVX512DQ && <round_saeonly_modev8sf_condition>"
> +(define_insn
> "fix<fixunssuffix>_trunc<ssePSmode2lower><mode>2<mask_name><round_saeonly_name>"
> + [(set (match_operand:VI8_256_512 0 "register_operand" "=v")
> + (any_fix:VI8_256_512
> + (match_operand:<ssePSmode2> 1 "<round_saeonly_nimm_predicate>"
> "<round_saeonly_constraint>")))]
> + "TARGET_AVX512DQ && <round_saeonly_mode512bit_condition>"
> "vcvttps2<fixsuffix>qq\t{<round_saeonly_mask_op2>%1,
> %0<mask_operand2>|%0<mask_operand2>, %1<round_saeonly_mask_op2>}"
> [(set_attr "type" "ssecvt")
> (set_attr "prefix" "evex")
> - (set_attr "mode" "<sseintvecmode3>")])
> + (set_attr "mode" "<sseinsnmode>")])
>
> (define_insn
> "unspec_avx512dq_fix<vcvtt_uns_suffix>_truncv2sfv2di2<mask_name>"
> [(set (match_operand:V2DI 0 "register_operand" "=v")
> diff --git a/gcc/config/i386/subst.md b/gcc/config/i386/subst.md
> index 7a9b697e0f6..40fb92094d2 100644
> --- a/gcc/config/i386/subst.md
> +++ b/gcc/config/i386/subst.md
> @@ -211,7 +211,6 @@ (define_subst_attr "round_mode512bit_condition" "round"
> "1" "(<MODE>mode == V16S
> || <MODE>mode
> == V16SImode
> || <MODE>mode
> == V32HFmode)")
>
> -(define_subst_attr "round_modev8sf_condition" "round" "1" "(<MODE>mode ==
> V8SFmode)")
> (define_subst_attr "round_modev4sf_condition" "round" "1" "(<MODE>mode ==
> V4SFmode)")
> (define_subst_attr "round_codefor" "round" "*" "")
> (define_subst_attr "round_opnum" "round" "5" "6")
> @@ -257,7 +256,6 @@ (define_subst_attr "round_saeonly_mode512bit_condition"
> "round_saeonly" "1" "(<M
>
> || <MODE>mode == V16SImode
>
> || <MODE>mode == V32HFmode)")
>
> -(define_subst_attr "round_saeonly_modev8sf_condition" "round_saeonly" "1"
> "(<MODE>mode == V8SFmode)")
>
> (define_subst "round_saeonly"
> [(set (match_operand:SUBST_A 0)
> --
> 2.31.1
>
--
BR,
Hongtao
