On Thu, 20 Jun 2024, YunQiang Su wrote: > MIPSr6 removes condition trap instructions with imm, so the instruction > like `teq $2,imm` will be converted to > li $at, imm > teq $2, $at > > The current version of Gas cannot detect if imm is zero, and output > teq $2, $0 > Let's do it in GCC.
This description should state that the change is a fix for an actual bug in GCC where the output pattern does not match the constraints supplied, and what consequences this has that the fix addressed. There is no `imm' in the general sense here, just the special case of zero. The missed optimisation in GAS, which used not to trigger pre-R6, is irrelevant from this change's point of view and just adds noise. I'm surprised that it worked even in the first place, as I reckon GCC is supposed to emit regular MIPS code in the `.set nomacro' mode nowadays, which is the only way to guarantee that instruction lengths known to GCC do not accidentally disagree with what the assembler has produced, such as in the case of the bug your change has addressed. Overall ISTM there is no need for distinct insns for ISA_HAS_COND_TRAPI and !ISA_HAS_COND_TRAPI cases each and this would better be sorted with predicates and constraints, especially as the output pattern is the same in both cases anyway. This would prevent special-casing from being needed in `mips_expand_conditional_trap' as well. Maciej
