Thanks for taking a look! Things have changed after I posted this patch and LLVM doesn't support this option now, so I think we don't need this patch any more.
Please see this PR and its references: https://github.com/riscv-non-isa/riscv-c-api-doc/pull/62. On 2024/6/25 2:17, Palmer Dabbelt wrote: > On Fri, 22 Dec 2023 01:23:13 PST (-0800), wangpengcheng...@bytedance.com > wrote: >> These two options are negative alias of -m[no-]strict-align. >> >> This matches LLVM implmentation. >> >> gcc/ChangeLog: >> >> * config/riscv/riscv.opt: Add option alias. >> >> gcc/testsuite/ChangeLog: >> >> * gcc.target/riscv/predef-align-10.c: New test. >> * gcc.target/riscv/predef-align-7.c: New test. >> * gcc.target/riscv/predef-align-8.c: New test. >> * gcc.target/riscv/predef-align-9.c: New test. >> >> Signed-off-by: Wang Pengcheng > > Sorry for being slow here. With the scalar/vector alignment split we're > cleaning up a bunch of these LLVM/GCC differences, and we're waiting for > the LLVM folks to decide how these are going to behave. LLVM will > release well before GCC does, so we've got some time. > > So this isn't lost, just slow. > >> --- >> gcc/config/riscv/riscv.opt | 4 ++++ >> gcc/testsuite/gcc.target/riscv/predef-align-10.c | 16 ++++++++++++++++ >> gcc/testsuite/gcc.target/riscv/predef-align-7.c | 15 +++++++++++++++ >> gcc/testsuite/gcc.target/riscv/predef-align-8.c | 16 ++++++++++++++++ >> gcc/testsuite/gcc.target/riscv/predef-align-9.c | 15 +++++++++++++++ >> 5 files changed, 66 insertions(+) >> create mode 100644 gcc/testsuite/gcc.target/riscv/predef-align-10.c >> create mode 100644 gcc/testsuite/gcc.target/riscv/predef-align-7.c >> create mode 100644 gcc/testsuite/gcc.target/riscv/predef-align-8.c >> create mode 100644 gcc/testsuite/gcc.target/riscv/predef-align-9.c >> >> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt >> index cf207d4dcdf..1e22998ce6e 100644 >> --- a/gcc/config/riscv/riscv.opt >> +++ b/gcc/config/riscv/riscv.opt >> @@ -116,6 +116,10 @@ mstrict-align >> Target Mask(STRICT_ALIGN) Save >> Do not generate unaligned memory accesses. >> >> +munaligned-access >> +Target Alias(mstrict-align) NegativeAlias >> +Enable unaligned memory accesses. >> + >> Enum >> Name(code_model) Type(enum riscv_code_model) >> Known code models (for use with the -mcmodel= option): >> diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-10.c >> b/gcc/testsuite/gcc.target/riscv/predef-align-10.c >> new file mode 100644 >> index 00000000000..c86b2c7a5ed >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/riscv/predef-align-10.c >> @@ -0,0 +1,16 @@ >> +/* { dg-do compile } */ >> +/* { dg-options "-mtune=rocket -munaligned-access" } */ >> + >> +int main() { >> + >> +/* rocket default is cpu tune param misaligned access slow */ >> +#if !defined(__riscv_misaligned_slow) >> +#error "__riscv_misaligned_slow is not set" >> +#endif >> + >> +#if defined(__riscv_misaligned_avoid) || >> defined(__riscv_misaligned_fast) >> +#error "__riscv_misaligned_avoid or __riscv_misaligned_fast is >> unexpectedly set" >> +#endif >> + >> + return 0; >> +} >> diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-7.c >> b/gcc/testsuite/gcc.target/riscv/predef-align-7.c >> new file mode 100644 >> index 00000000000..405f3686c2e >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/riscv/predef-align-7.c >> @@ -0,0 +1,15 @@ >> +/* { dg-do compile } */ >> +/* { dg-options "-mtune=thead-c906 -mno-unaligned-access" } */ >> + >> +int main() { >> + >> +#if !defined(__riscv_misaligned_avoid) >> +#error "__riscv_misaligned_avoid is not set" >> +#endif >> + >> +#if defined(__riscv_misaligned_fast) || defined(__riscv_misaligned_slow) >> +#error "__riscv_misaligned_fast or __riscv_misaligned_slow is >> unexpectedly >> set" >> +#endif >> + >> + return 0; >> +} >> diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-8.c >> b/gcc/testsuite/gcc.target/riscv/predef-align-8.c >> new file mode 100644 >> index 00000000000..64072c04a47 >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/riscv/predef-align-8.c >> @@ -0,0 +1,16 @@ >> +/* { dg-do compile } */ >> +/* { dg-options "-mtune=thead-c906 -munaligned-access" } */ >> + >> +int main() { >> + >> +/* thead-c906 default is cpu tune param misaligned access fast */ >> +#if !defined(__riscv_misaligned_fast) >> +#error "__riscv_misaligned_fast is not set" >> +#endif >> + >> +#if defined(__riscv_misaligned_avoid) || >> defined(__riscv_misaligned_slow) >> +#error "__riscv_misaligned_avoid or __riscv_misaligned_slow is >> unexpectedly set" >> +#endif >> + >> + return 0; >> +} >> diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-9.c >> b/gcc/testsuite/gcc.target/riscv/predef-align-9.c >> new file mode 100644 >> index 00000000000..f5418de87cf >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/riscv/predef-align-9.c >> @@ -0,0 +1,15 @@ >> +/* { dg-do compile } */ >> +/* { dg-options "-mtune=rocket -mno-unaligned-access" } */ >> + >> +int main() { >> + >> +#if !defined(__riscv_misaligned_avoid) >> +#error "__riscv_misaligned_avoid is not set" >> +#endif >> + >> +#if defined(__riscv_misaligned_fast) || defined(__riscv_misaligned_slow) >> +#error "__riscv_misaligned_fast or __riscv_misaligned_slow is >> unexpectedly >> set" >> +#endif >> + >> + return 0; >> +}
