пн, 17 июн. 2024 г. в 15:43, Richard Earnshaw (lists)
<richard.earns...@arm.com>:
> I like the idea behind this patch, but I think I'd try first doing this as a
> peephole2 rule to rewrite the address in this case. That has the additional
> advantage that we then estimate the size of the instruction more accurately.
Indeed, I tried it and it seems to work, although sometimes it does
odd things that I can't explain, e.g:
define_insn patch define_peephole2 patch
... ...
ldmia r0!, {r4, r5} movs r3, r0
ldmia r1!, {r2, r3} ldmia r3!, {r4, r5}
movs r0, r7 movs r0, r7
... ldr r2, [r1, #0]
ldr r3, [r1, #4]
# r1 unused later on
...
But in general it finds a little bit more cases where ldmia/stmia can
be applied.
> > 2. Might it be profitable for thumb2?
> I think it would then be easy to extend this to thumb2 as well if it looks
> like a win (perhaps only for -Os in the thumb2 case).
Sounds good, I'll look at it later.
> For testing, I'd start with something like
> gcc/testsuite/gcc.target/arm/thumb-andsi.c as a template and adapt that for
> your specific case. Matching something like "ldmia\tr[0-7]!," should be
> enough.
I'll send the v2 patch with test case(s) soon.
BR, Siarhei
