Re: [PATCH V2 1/2] RISC-V: Fix vwsll combine on rv32 targets

[Robin Dapp]

> diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
> index 6a2eabbd854..29916adb62b 100644
> --- a/gcc/config/riscv/autovec-opt.md
> +++ b/gcc/config/riscv/autovec-opt.md
> @@ -1517,8 +1517,7 @@ (define_insn_and_split "*vwsll_zext1_scalar_<mode>"
>    "&& 1"
>    [(const_int 0)]
>    {
> -    if (GET_CODE (operands[2]) == SUBREG)
> -      operands[2] = SUBREG_REG (operands[2]);
> +    operands[2] = gen_lowpart (Pmode, operands[2]);
>      insn_code icode = code_for_pred_vwsll_scalar (<MODE>mode);
>      riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
>      DONE;

Please also correct it in the other expander (_trunc_).
OK with that change if the testsuite still looks ok :)

Regards
 Robin