On 5/22/24 4:58 AM, Richard Biener wrote:
RISC-V CI didn't trigger (not sure what magic is required). Both ARM and AARCH64 show that the "Vectorizing stmts using SLP" are a bit fragile because we sometimes cancel SLP becuase we want to use load/store-lanes.
The RISC-V tag on the subject line is the trigger. Jeff
