Trying --enable-build-with-cxx revealed a build regression for
cris-elf from the recent atomic support bits. Tested the same,
no regressions.
Casting those INTVAL's would've been a tiny bit uglier than
using a temp, thus. <rant>Hey, those were stashed there as ints
so what's wrong with passing them as that! And making "and" a
reserved word, what's up with that? Is that supposed to be
easier on the eye or to write than "&"? Stupid C++.</rant>. ;)
Actually, I'm on the fence FWIW, as long as you don't try to
reindent or force a new formatting standard.
Committed.
gcc:
Fix CRIS build errors with --enable-build-with-cxx.
* config/cris/cris.c (cris_emit_trap_for_misalignment): Rename
variable "and" to "andop".
* config/cris/sync.md ("atomic_fetch_<atomic_op_name><mode>"): Use
temporary variable for memory model, passing C++-type-correct
parameter type to expand_mem_thread_fence.
("atomic_compare_and_swap<mode>"): Ditto.
Index: gcc/config/cris/sync.md
===================================================================
--- gcc/config/cris/sync.md (revision 188355)
+++ gcc/config/cris/sync.md (working copy)
@@ -88,14 +88,16 @@ (define_expand "atomic_fetch_<atomic_op_
(atomic_op:BWD (match_dup 0) (match_dup 1))]
""
{
+ enum memmodel mmodel = (enum memmodel) INTVAL (operands[3]);
+
if (<MODE>mode != QImode && TARGET_TRAP_UNALIGNED_ATOMIC)
cris_emit_trap_for_misalignment (operands[1]);
- expand_mem_thread_fence (INTVAL (operands[3]));
+ expand_mem_thread_fence (mmodel);
emit_insn (gen_cris_atomic_fetch_<atomic_op_name><mode>_1 (operands[0],
operands[1],
operands[2]));
- expand_mem_thread_fence (INTVAL (operands[3]));
+ expand_mem_thread_fence (mmodel);
DONE;
})
@@ -189,16 +191,18 @@ (define_expand "atomic_compare_and_swap<
(match_operand 7)]
""
{
+ enum memmodel mmodel = (enum memmodel) INTVAL (operands[6]);
+
if (<MODE>mode != QImode && TARGET_TRAP_UNALIGNED_ATOMIC)
cris_emit_trap_for_misalignment (operands[2]);
- expand_mem_thread_fence (INTVAL (operands[6]));
+ expand_mem_thread_fence (mmodel);
emit_insn (gen_cris_atomic_compare_and_swap<mode>_1 (operands[0],
operands[1],
operands[2],
operands[3],
operands[4]));
- expand_mem_thread_fence (INTVAL (operands[6]));
+ expand_mem_thread_fence (mmodel);
DONE;
})
Index: gcc/config/cris/cris.c
===================================================================
--- gcc/config/cris/cris.c (revision 188355)
+++ gcc/config/cris/cris.c (working copy)
@@ -1929,7 +1929,7 @@ cris_simple_epilogue (void)
void
cris_emit_trap_for_misalignment (rtx mem)
{
- rtx addr, reg, ok_label, and, jmp;
+ rtx addr, reg, ok_label, andop, jmp;
int natural_alignment;
gcc_assert (MEM_P (mem));
@@ -1941,8 +1941,8 @@ cris_emit_trap_for_misalignment (rtx mem
/* This will yield a btstq without a separate register used, usually -
with the exception for PRE hoisting the "and" but not the branch
around the trap: see gcc.dg/target/cris/sync-3s.c. */
- and = gen_rtx_AND (Pmode, reg, GEN_INT (natural_alignment - 1));
- emit_cmp_and_jump_insns (force_reg (SImode, and), const0_rtx, EQ,
+ andop = gen_rtx_AND (Pmode, reg, GEN_INT (natural_alignment - 1));
+ emit_cmp_and_jump_insns (force_reg (SImode, andop), const0_rtx, EQ,
NULL_RTX, Pmode, 1, ok_label);
jmp = get_last_insn ();
gcc_assert (JUMP_P (jmp));
brgds, H-P
