on 2024/2/27 10:13, Peter Bergner wrote: > On 2/26/24 7:55 PM, Kewen.Lin wrote: >> on 2024/2/26 23:07, Peter Bergner wrote: >>> so I think we should use both Jeevitha's predicate change and >>> your operands[1] change. >> >> Since either the original predicate change or operands[1] change >> can fix this issue, I think it's implied that only either of them >> is enough, so we can remove "else if (!REG_P (op1))" arm (or even >> replaced with one else arm to assert REG_P (op1))? > > splat_input_operand allows, mem, reg and subreg, so I don't think > we can just assert on REG_P (op1), since op1 could be a subreg.
ah, you are right! I missed the "subreg". > I do agree we can remove the "if (!REG_P (op1))" test on the else > branch, since force_reg() has an early exit for regs, so a simple: > > ... > else > operands[1] = force_reg (<VSX_D:VEC_base>mode, op1); > > ..should work. Yes! > > > > >> Good point, or maybe just an explicit -mvsx like some existing ones, which >> can avoid to only test some fixed cpu type. > > If a simple "-O1 -vsx" is enough to expose the ICE on an unpacthed > compiler and a PASS on a patched compiler, then I'm all for it. > Jeevitha, can you try confirming that? Jeevitha, can you also check why we have the different behavior on GCC 11 when you get time? GCC 12 has new built-in framework, so this ICE gets exposed, but IMHO it would still be good to double check the previous behavior is due to some miss support or some other latent bug. Thanks in advance! BR, Kewen
