Hello Michael: On 17/01/24 7:58 pm, Michael Matz wrote: > Hello, > > On Wed, 17 Jan 2024, Ajit Agarwal wrote: > >>> first is even, since OOmode is only ok for even vsx register and its >>> size makes it take two consecutive vsx registers. >>> >>> Hi Peter, is my understanding correct? >>> >> >> I tried all the combination in the past RA is not allocating sequential >> register. I dont see any such code in RA that generates sequential >> registers. > > See HARD_REGNO_NREGS. If you form a pseudo of a mode that's larger than a > native-sized hardreg (and the target is correctly set up) then the RA will > allocate the correct number of hardregs (consecutively) for this pseudo. > This is what Kewen was referring to by mentioning the OOmode for the new > hypothetical pseudo. The individual parts of such pseudo will then need > to use subreg to access them. > > So, when you work before RA you simply will transform this (I'm going to > use SImode and DImode for demonstration): > > (set (reg:SI x) (mem:SI (addr))) > (set (reg:SI y) (mem:SI (addr+4))) > ... > ( ...use1... (reg:SI x)) > ( ...use2... (reg:SI y)) > > into this: > > (set (reg:DI z) (mem:DI (addr))) > ... > ( ...use1... (subreg:SI (reg:DI z) 0)) > ( ...use2... (subreg:SI (reg:DI z) 4)) > > For this to work the target needs to accept the (subreg...) in certain > operands of instruction patterns, which I assume was what Kewen also > referred to. The register allocator will then assign hardregs X and X+1 > to the pseudo-reg 'z'. (Assuming that DImode is okay for hardreg X, and > HARD_REGNO_NREGS says that it needs two hardregs to hold DImode). > > It will also replace the subregs by their appropriate concrete hardreg. > > It seems your problems stem from trying to place your new pass somewhere > within the register-allocation pipeline, rather than simply completely > before. >
Thanks for the suggestions. It worked and with above changes sequential registers are generated by RA pass. I am working on common infrastructure with AARCH64 for register pairs loads and stores pass. Thanks & Regards Ajit > > Ciao, > Michael.
