OK, thanks :)
On Thu, Jan 18, 2024 at 4:17 PM Jakub Jelinek <[email protected]> wrote: > > Hi! > > As I wrote recently, Bool is an undocumented unsupported keyword, as > can be seen by > grep Bool doc/options.texi *.awk > The option parsing just parses and ignores all keywords it doesn't handle. > But, because it isn't a supported keyword, I think we shouldn't have it in > *.opt files, because that just means people copy it over to other places > even when it doesn't have any effect. > > Tested with a cross to riscv64-linux, none of the generated > options.{h,cc} options-{save,urls}.cc > files change with the patch, only optionlist does (but that is just > used as a source for those files). > > Ok for trunk? > > 2024-01-18 Jakub Jelinek <[email protected]> > > * config/riscv/riscv.opt (mshorten-memrefs, mrelax, mcsr-check, > minline-strcmp, minline-strncmp, minline-strlen, > -param=riscv-vector-abi): Remove Bool keywords. > > --- gcc/config/riscv/riscv.opt.jj 2024-01-18 08:44:33.441919890 +0100 > +++ gcc/config/riscv/riscv.opt 2024-01-18 08:58:22.788359898 +0100 > @@ -103,7 +103,7 @@ Target Mask(SAVE_RESTORE) > Use smaller but slower prologue and epilogue code. > > mshorten-memrefs > -Target Bool Var(riscv_mshorten_memrefs) Init(1) > +Target Var(riscv_mshorten_memrefs) Init(1) > Convert BASE + LARGE_OFFSET addresses to NEW_BASE + SMALL_OFFSET to allow > more > memory accesses to be generated as compressed instructions. Currently > targets > 32-bit integer load/stores. > @@ -134,12 +134,12 @@ Target Mask(EXPLICIT_RELOCS) > Use %reloc() operators, rather than assembly macros, to load addresses. > > mrelax > -Target Bool Var(riscv_mrelax) Init(1) > +Target Var(riscv_mrelax) Init(1) > Take advantage of linker relaxations to reduce the number of instructions > required to materialize symbol addresses. > > mcsr-check > -Target Bool Var(riscv_mcsr_check) Init(0) > +Target Var(riscv_mcsr_check) Init(0) > Enable the CSR checking for the ISA-dependent CRS and the read-only CSR. > The ISA-dependent CSR are only valid when the specific ISA is set. The > read-only CSR can not be written by the CSR instructions. > @@ -483,15 +483,15 @@ Target Var(TARGET_INLINE_SUBWORD_ATOMIC) > Always inline subword atomic operations. > > minline-strcmp > -Target Bool Var(riscv_inline_strcmp) Init(0) > +Target Var(riscv_inline_strcmp) Init(0) > Inline strcmp calls if possible. > > minline-strncmp > -Target Bool Var(riscv_inline_strncmp) Init(0) > +Target Var(riscv_inline_strncmp) Init(0) > Inline strncmp calls if possible. > > minline-strlen > -Target Bool Var(riscv_inline_strlen) Init(0) > +Target Var(riscv_inline_strlen) Init(0) > Inline strlen calls if possible. > > -param=riscv-strcmp-inline-limit= > @@ -542,7 +542,7 @@ madjust-lmul-cost > Target Var(TARGET_ADJUST_LMUL_COST) Init(0) > > -param=riscv-vector-abi > -Target Undocumented Bool Var(riscv_vector_abi) Init(0) > +Target Undocumented Var(riscv_vector_abi) Init(0) > Enable the use of vector registers for function arguments and return value. > This is an experimental switch and may be subject to change in the future. > > > Jakub >
