This patch fixes SPEC2017 cam4 mismatch issue due to we miss has compatible
check
for conflict vsetvl fusion.
Buggy assembler before this patch:
.L69:
vsetvli a5,s1,e8,mf4,ta,ma -> buggy vsetvl
vsetivli zero,8,e8,mf2,ta,ma
vmv.v.i v1,0
vse8.v v1,0(a5)
j .L37
.L68:
vsetvli a5,s1,e8,mf4,ta,ma -> buggy vsetvl
vsetivli zero,8,e8,mf2,ta,ma
addi a3,a5,8
vmv.v.i v1,0
vse8.v v1,0(a5)
vse8.v v1,0(a3)
addi a4,a4,-16
li a3,8
bltu a4,a3,.L37
j .L69
.L67:
vsetivli zero,8,e8,mf2,ta,ma
vmv.v.i v1,0
vse8.v v1,0(a5)
addi a5,sp,56
vse8.v v1,0(a5)
addi s4,sp,64
addi a3,sp,72
vse8.v v1,0(s4)
vse8.v v1,0(a3)
addi a4,a4,-32
li a3,16
bltu a4,a3,.L36
j .L68
After this patch:
.L63:
ble s1,zero,.L49
slli a4,s1,3
li a3,32
addi a5,sp,48
bltu a4,a3,.L62
vsetivli zero,8,e8,mf2,ta,ma
vmv.v.i v1,0
vse8.v v1,0(a5)
addi a5,sp,56
vse8.v v1,0(a5)
addi s4,sp,64
addi a3,sp,72
vse8.v v1,0(s4)
addi a4,a4,-32
addi a5,sp,80
vse8.v v1,0(a3)
.L35:
li a3,16
bltu a4,a3,.L36
addi a3,a5,8
vmv.v.i v1,0
addi a4,a4,-16
vse8.v v1,0(a5)
addi a5,a5,16
vse8.v v1,0(a3)
.L36:
li a3,8
bltu a4,a3,.L37
vmv.v.i v1,0
vse8.v v1,0(a5)
Tested on both RV32/RV64 no regression, Ok for trunk ?
PR target/113429
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info):
Fix conflict vsetvl fusion.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c: Adapt test.
* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c: Ditto.
---
gcc/config/riscv/riscv-vsetvl.cc | 39 +++++++++++--------
.../riscv/rvv/vsetvl/vlmax_conflict-4.c | 5 +--
.../riscv/rvv/vsetvl/vlmax_conflict-5.c | 10 ++---
3 files changed, 28 insertions(+), 26 deletions(-)
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index df7ed149388..76e3d2eb471 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -2254,6 +2254,22 @@ private:
return true;
}
+ bool has_compatible_reaching_vsetvl_p (vsetvl_info info)
+ {
+ unsigned int index;
+ sbitmap_iterator sbi;
+ EXECUTE_IF_SET_IN_BITMAP (m_vsetvl_def_in[info.get_bb ()->index ()], 0,
+ index, sbi)
+ {
+ const auto prev_info = *m_vsetvl_def_exprs[index];
+ if (!prev_info.valid_p ())
+ continue;
+ if (m_dem.compatible_p (prev_info, info))
+ return true;
+ }
+ return false;
+ }
+
bool preds_all_same_avl_and_ratio_p (const vsetvl_info &curr_info)
{
gcc_assert (
@@ -3075,22 +3091,8 @@ pre_vsetvl::earliest_fuse_vsetvl_info ()
{
vsetvl_info new_curr_info = curr_info;
new_curr_info.set_bb (crtl->ssa->bb (eg->dest));
- bool has_compatible_p = false;
- unsigned int def_expr_index;
- sbitmap_iterator sbi2;
- EXECUTE_IF_SET_IN_BITMAP (
- m_vsetvl_def_in[new_curr_info.get_bb ()->index ()], 0,
- def_expr_index, sbi2)
- {
- vsetvl_info &prev_info = *m_vsetvl_def_exprs[def_expr_index];
- if (!prev_info.valid_p ())
- continue;
- if (m_dem.compatible_p (prev_info, new_curr_info))
- {
- has_compatible_p = true;
- break;
- }
- }
+ bool has_compatible_p
+ = has_compatible_reaching_vsetvl_p (new_curr_info);
if (!has_compatible_p)
{
if (dump_file && (dump_flags & TDF_DETAILS))
@@ -3146,7 +3148,10 @@ pre_vsetvl::earliest_fuse_vsetvl_info ()
&& !m_dem.compatible_p (prev_info, curr_info))
{
/* Cancel lift up if probabilities are equal. */
- if (successors_probability_equal_p (eg->src))
+ if (successors_probability_equal_p (eg->src)
+ || (dest_block_info.probability
+ > src_block_info.probability
+ && !has_compatible_reaching_vsetvl_p (curr_info)))
{
if (dump_file && (dump_flags & TDF_DETAILS))
{
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c
index 28ffe2c687a..dedbc94fb29 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c
@@ -23,7 +23,6 @@ void f (int32_t * restrict in, int32_t * restrict out, size_t
n, size_t cond, si
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target {
no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target {
no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 3 { target {
no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+\.L[0-9]:+} 1 {
target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli} 5 { target { no-opts "-O0"
no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" } } } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 1 { target {
no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0"
no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c
index cd94fdae4b4..26db192d836 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c
@@ -17,15 +17,13 @@ void f (int32_t * restrict in, int32_t * restrict out,
size_t n, size_t cond, si
vuint16mf2_t v = *(vuint16mf2_t*)(in + i + 300);
*(vuint16mf2_t*)(out + i + 300) = v;
} else {
- vbool1_t v = *(vbool1_t*)(in + i + 400);
- *(vbool1_t*)(out + i + 400) = v;
+ vint8mf8_t v = *(vint8mf8_t*)(in + i + 400);
+ *(vint8mf8_t*)(out + i + 400) = v;
}
}
}
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 { target {
no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target {
no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target {
no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 1 { target {
no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli} 4 { target { no-opts "-O0"
no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" } } } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target {
no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0"
no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" } } } } */
--
2.36.3
