chenxiaolong writes:
> In order to improve and check the function of vector quantization in
> LoongArch architecture, tests on vector instruction set are provided
> in target-support.exp.
>
> gcc/testsuite/ChangeLog:
>
> * lib/target-supports.exp:Add LoongArch to the list of supported
> targets.
^ Should be a space after ":".
> ---
> gcc/testsuite/lib/target-supports.exp | 219 +++++++++++++++++++-------
> 1 file changed, 161 insertions(+), 58 deletions(-)
>
> diff --git a/gcc/testsuite/lib/target-supports.exp
> b/gcc/testsuite/lib/target-supports.exp
> index 14e3e119792..b90aaf8cabe 100644
> --- a/gcc/testsuite/lib/target-supports.exp
> +++ b/gcc/testsuite/lib/target-supports.exp
> @@ -3811,7 +3811,11 @@ proc add_options_for_bfloat16 { flags } {
> # (fma, fms, fnma, and fnms) for both float and double.
>
> proc check_effective_target_scalar_all_fma { } {
> - return [istarget aarch64*-*-*]
> + if { [istarget aarch64*-*-*]
Trailing whitespace.
> + || [istarget loongarch*-*-*]} {
> + return 1
> + }
> + return 0
> }
>
> # Return 1 if the target supports compiling fixed-point,
> @@ -4017,7 +4021,7 @@ proc check_effective_target_vect_cmdline_needed { } {
> || ([istarget arm*-*-*] && [check_effective_target_arm_neon])
> || [istarget aarch64*-*-*]
> || [istarget amdgcn*-*-*]
> - || [istarget riscv*-*-*]} {
> + || [istarget riscv*-*-*] } {
Misses something ?
> return 0
> } else {
> return 1
> @@ -4047,6 +4051,8 @@ proc check_effective_target_vect_int { } {
> && [check_effective_target_s390_vx])
> || ([istarget riscv*-*-*]
> && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx])
> }}]
> }
>
> @@ -4176,7 +4182,9 @@ proc check_effective_target_vect_intfloat_cvt { } {
> || ([istarget s390*-*-*]
> && [check_effective_target_s390_vxe2])
> || ([istarget riscv*-*-*]
> - && [check_effective_target_riscv_v]) }}]
> + && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx]) }}]
> }
>
> # Return 1 if the target supports signed double->int conversion
> @@ -4197,7 +4205,9 @@ proc check_effective_target_vect_doubleint_cvt { } {
> || ([istarget s390*-*-*]
> && [check_effective_target_s390_vx])
> || ([istarget riscv*-*-*]
> - && [check_effective_target_riscv_v]) }}]
> + && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx]) }}]
> }
>
> # Return 1 if the target supports signed int->double conversion
> @@ -4218,7 +4228,9 @@ proc check_effective_target_vect_intdouble_cvt { } {
> || ([istarget s390*-*-*]
> && [check_effective_target_s390_vx])
> || ([istarget riscv*-*-*]
> - && [check_effective_target_riscv_v]) }}]
> + && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx]) }}]
> }
>
> #Return 1 if we're supporting __int128 for target, 0 otherwise.
> @@ -4251,7 +4263,9 @@ proc check_effective_target_vect_uintfloat_cvt { } {
> || ([istarget s390*-*-*]
> && [check_effective_target_s390_vxe2])
> || ([istarget riscv*-*-*]
> - && [check_effective_target_riscv_v]) }}]
> + && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx]) }}]
> }
>
>
> @@ -4270,7 +4284,9 @@ proc check_effective_target_vect_floatint_cvt { } {
> || ([istarget s390*-*-*]
> && [check_effective_target_s390_vxe2])
> || ([istarget riscv*-*-*]
> - && [check_effective_target_riscv_v]) }}]
> + && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx]) }}]
> }
>
> # Return 1 if the target supports unsigned float->int conversion
> @@ -4287,7 +4303,9 @@ proc check_effective_target_vect_floatuint_cvt { } {
> || ([istarget s390*-*-*]
> && [check_effective_target_s390_vxe2])
> || ([istarget riscv*-*-*]
> - && [check_effective_target_riscv_v]) }}]
> + && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx]) }}]
> }
>
> # Return 1 if the target supports vector integer char -> long long extend
> optab
> @@ -4296,7 +4314,9 @@ proc check_effective_target_vect_floatuint_cvt { } {
> proc check_effective_target_vect_ext_char_longlong { } {
> return [check_cached_effective_target_indexed vect_ext_char_longlong {
> expr { ([istarget riscv*-*-*]
> - && [check_effective_target_riscv_v]) }}]
> + && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx]) }}]
> }
>
> # Return 1 if peeling for alignment might be profitable on the target
> @@ -7420,7 +7440,9 @@ proc check_effective_target_vect_shift { } {
> && [check_effective_target_s390_vx])
> || [istarget amdgcn-*-*]
> || ([istarget riscv*-*-*]
> - && [check_effective_target_riscv_v]) }}]
> + && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx]) }}]
> }
>
> # Return 1 if the target supports hardware vector shift by register
> operation.
> @@ -7432,6 +7454,8 @@ proc check_effective_target_vect_var_shift { } {
> || [istarget aarch64*-*-*]
> || ([istarget riscv*-*-*]
> && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx])
> }}]
> }
>
> @@ -7448,7 +7472,9 @@ proc check_effective_target_whole_vector_shift { } {
> && [check_effective_target_s390_vx])
> || [istarget amdgcn-*-*]
> || ([istarget riscv*-*-*]
> - && [check_effective_target_riscv_v]) } {
> + && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx]) } {
> set answer 1
> } else {
> set answer 0
> @@ -7465,6 +7491,7 @@ proc check_effective_target_vect_bswap { } {
> expr { ([istarget aarch64*-*-*]
> || [is-effective-target arm_neon]
> || [istarget amdgcn-*-*])
> + || [istarget loongarch*-*-*]
> || ([istarget s390*-*-*]
> && [check_effective_target_s390_vx]) }}]
> }
> @@ -7478,7 +7505,9 @@ proc check_effective_target_vect_bool_cmp { } {
> || [istarget aarch64*-*-*]
> || [is-effective-target arm_neon]
> || ([istarget riscv*-*-*]
> - && [check_effective_target_riscv_v]) }}]
> + && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx]) }}]
> }
>
> # Return 1 if the target supports addition of char vectors for at least
> @@ -7501,6 +7530,8 @@ proc check_effective_target_vect_char_add { } {
> && [check_effective_target_s390_vx])
> || ([istarget riscv*-*-*]
> && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx])
> }}]
> }
>
> @@ -7517,7 +7548,9 @@ proc check_effective_target_vect_shift_char { } {
> && [check_effective_target_s390_vx])
> || [istarget amdgcn-*-*]
> || ([istarget riscv*-*-*]
> - && [check_effective_target_riscv_v]) }}]
> + && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx]) }}]
> }
>
> # Return 1 if the target supports hardware vectors of long, 0 otherwise.
> @@ -7538,7 +7571,9 @@ proc check_effective_target_vect_long { } {
> && [check_effective_target_s390_vx])
> || [istarget amdgcn-*-*]
> || ([istarget riscv*-*-*]
> - && [check_effective_target_riscv_v]) } {
> + && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx]) } {
> set answer 1
> } else {
> set answer 0
> @@ -7568,7 +7603,9 @@ proc check_effective_target_vect_float { } {
> && [check_effective_target_s390_vxe])
> || [istarget amdgcn-*-*]
> || ([istarget riscv*-*-*]
> - && [check_effective_target_riscv_v]) }}]
> + && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx]) }}]
> }
>
> # Return 1 if the target supports hardware vectors of float without
> @@ -7599,7 +7636,9 @@ proc check_effective_target_vect_double { } {
> && [check_effective_target_s390_vx])
> || [istarget amdgcn-*-*]
> || ([istarget riscv*-*-*]
> - && [check_effective_target_riscv_v])} }]
> + && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx]) }}]
> }
>
> # Return 1 if the target supports conditional addition, subtraction,
> @@ -7627,7 +7666,9 @@ proc check_effective_target_vect_long_long { } {
> && [check_effective_target_has_arch_pwr8])
> || [istarget aarch64*-*-*]
> || ([istarget riscv*-*-*]
> - && [check_effective_target_riscv_v])}}]
> + && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx])}}]
> }
>
>
> @@ -7682,7 +7723,9 @@ proc check_effective_target_vect_perm { } {
> && [check_effective_target_s390_vx])
> || [istarget amdgcn-*-*]
> || ([istarget riscv*-*-*]
> - && [check_effective_target_riscv_v]) }}]
> + && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx]) }}]
> }
>
> # Return 1 if, for some VF:
> @@ -7777,7 +7820,9 @@ proc check_effective_target_vect_perm_byte { } {
> && [check_effective_target_s390_vx])
> || [istarget amdgcn-*-*]
> || ([istarget riscv*-*-*]
> - && [check_effective_target_riscv_v]) }}]
> + && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx]) }}]
> }
>
> # Return 1 if the target supports SLP permutation of 3 vectors when each
> @@ -7808,7 +7853,9 @@ proc check_effective_target_vect_perm_short { } {
> && [check_effective_target_s390_vx])
> || [istarget amdgcn-*-*]
> || ([istarget riscv*-*-*]
> - && [check_effective_target_riscv_v]) }}]
> + && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx]) }}]
> }
>
> # Return 1 if the target supports SLP permutation of 3 vectors when each
> @@ -7856,6 +7903,7 @@ proc check_effective_target_vect_widen_sum_hi_to_si { }
> {
> expr { [check_effective_target_vect_unpack]
> || [istarget powerpc*-*-*]
> || [istarget ia64-*-*]
> + || [istarget loongarch*-*-*]
> || [istarget riscv*-*-*] }}]
> }
>
> @@ -7871,7 +7919,8 @@ proc check_effective_target_vect_widen_sum_qi_to_hi { }
> {
> expr { [check_effective_target_vect_unpack]
> || [is-effective-target arm_neon]
> || [istarget ia64-*-*]
> - || [istarget riscv*-*-*] }}]
> + || [istarget riscv*-*-*]
> + || [istarget loongarch*-*-*] }}]
> }
>
> # Return 1 if the target plus current options supports a vector
> @@ -7882,6 +7931,7 @@ proc check_effective_target_vect_widen_sum_qi_to_hi { }
> {
> proc check_effective_target_vect_widen_sum_qi_to_si { } {
> return [check_cached_effective_target_indexed vect_widen_sum_qi_to_si {
> expr { [istarget powerpc*-*-*]
> + || [istarget loongarch*-*-*]
> || [istarget riscv*-*-*] }}]
> }
>
> @@ -7902,6 +7952,7 @@ proc check_effective_target_vect_widen_mult_qi_to_hi {
> } {
> || ([istarget aarch64*-*-*]
> && ![check_effective_target_aarch64_sve])
> || [is-effective-target arm_neon]
> + || [is-effective-target loongarch*-*-*]
> || ([istarget s390*-*-*]
> && [check_effective_target_s390_vx]))
> || [istarget amdgcn-*-*] }}]
> @@ -7926,6 +7977,7 @@ proc check_effective_target_vect_widen_mult_hi_to_si {
> } {
> && ![check_effective_target_aarch64_sve])
> || [istarget i?86-*-*] || [istarget x86_64-*-*]
> || [is-effective-target arm_neon]
> + || [is-effective-target loongarch*-*-*]
> || ([istarget s390*-*-*]
> && [check_effective_target_s390_vx]))
> || [istarget amdgcn-*-*] }}]
> @@ -7943,6 +7995,7 @@ proc
> check_effective_target_vect_widen_mult_qi_to_hi_pattern { } {
> && [check_effective_target_arm_little_endian])
> || ([istarget s390*-*-*]
> && [check_effective_target_s390_vx])
> + || [istarget loongarch*-*-*]
> || [istarget amdgcn-*-*] }}]
> }
>
> @@ -7955,6 +8008,7 @@ proc
> check_effective_target_vect_widen_mult_hi_to_si_pattern { } {
> return [check_cached_effective_target_indexed
> vect_widen_mult_hi_to_si_pattern {
> expr { [istarget powerpc*-*-*]
> || [istarget ia64-*-*]
> + || [istarget loongarch*-*-*]
> || [istarget i?86-*-*] || [istarget x86_64-*-*]
> || ([is-effective-target arm_neon]
> && [check_effective_target_arm_little_endian])
> @@ -7972,6 +8026,7 @@ proc
> check_effective_target_vect_widen_mult_si_to_di_pattern { } {
> return [check_cached_effective_target_indexed
> vect_widen_mult_si_to_di_pattern {
> expr { [istarget ia64-*-*]
> || [istarget i?86-*-*] || [istarget x86_64-*-*]
> + || [istarget loongarch*-*-*]
> || ([istarget s390*-*-*]
> && [check_effective_target_s390_vx]) }}]
> }
> @@ -7999,7 +8054,9 @@ proc check_effective_target_vect_sdot_qi { } {
> || ([istarget mips*-*-*]
> && [et-is-effective-target mips_msa])
> || ([istarget riscv*-*-*]
> - && [check_effective_target_riscv_v]) }}]
> + && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx]) }}]
> }
>
> # Return 1 if the target plus current options supports a vector
> @@ -8016,7 +8073,9 @@ proc check_effective_target_vect_udot_qi { } {
> || ([istarget mips*-*-*]
> && [et-is-effective-target mips_msa])
> || ([istarget riscv*-*-*]
> - && [check_effective_target_riscv_v]) }}]
> + && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx]) }}]
> }
>
> # Return 1 if the target plus current options supports a vector
> @@ -8045,7 +8104,9 @@ proc check_effective_target_vect_sdot_hi { } {
> || ([istarget mips*-*-*]
> && [et-is-effective-target mips_msa])
> || ([istarget riscv*-*-*]
> - && [check_effective_target_riscv_v]) }}]
> + && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx]) }}]
> }
>
> # Return 1 if the target plus current options supports a vector
> @@ -8059,7 +8120,9 @@ proc check_effective_target_vect_udot_hi { } {
> || ([istarget mips*-*-*]
> && [et-is-effective-target mips_msa])
> || ([istarget riscv*-*-*]
> - && [check_effective_target_riscv_v]) }}]
> + && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx]) }}]
> }
>
> # Return 1 if the target plus current options supports a vector
> @@ -8076,7 +8139,9 @@ proc check_effective_target_vect_usad_char { } {
> || ([istarget powerpc*-*-*]
> && [check_p9vector_hw_available])
> || ([istarget riscv*-*-*]
> - && [check_effective_target_riscv_v]) }}]
> + && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx]) }}]
> }
>
> # Return 1 if the target plus current options supports both signed
> @@ -8086,7 +8151,9 @@ proc check_effective_target_vect_avg_qi {} {
> return [expr { ([istarget aarch64*-*-*]
> && ![check_effective_target_aarch64_sve1_only])
> || ([istarget riscv*-*-*]
> - && [check_effective_target_riscv_v]) }]
> + && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx]) }]
> }
>
> # Return 1 if the target plus current options supports both signed
> @@ -8125,7 +8192,9 @@ proc check_effective_target_vect_pack_trunc { } {
> && [check_effective_target_s390_vx])
> || [istarget amdgcn*-*-*]
> || ([istarget riscv*-*-*]
> - && [check_effective_target_riscv_v]) }}]
> + && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx]) }}]
> }
>
> # Return 1 if the target plus current options supports a vector
> @@ -8147,7 +8216,9 @@ proc check_effective_target_vect_unpack { } {
> && [check_effective_target_s390_vx])
> || [istarget amdgcn*-*-*]
> || ([istarget riscv*-*-*]
> - && [check_effective_target_riscv_v]) }}]
> + && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx]) }}]
> }
>
> # Return 1 if the target plus current options does not guarantee
> @@ -8188,7 +8259,8 @@ proc check_effective_target_vect_hw_misalign { } {
> || ([istarget mips*-*-*] && [et-is-effective-target mips_msa])
> || ([istarget s390*-*-*]
> && [check_effective_target_s390_vx])
> - || ([istarget riscv*-*-*]) } {
> + || ([istarget riscv*-*-*])
> + || ([istarget loongarch*-*-*]) } {
> return 1
> }
> if { [istarget arm*-*-*]
> @@ -8807,7 +8879,8 @@ proc check_effective_target_vect_gather_load_ifn { } {
> proc check_effective_target_vect_scatter_store { } {
> return [expr { [check_effective_target_aarch64_sve]
> || [istarget amdgcn*-*-*]
> - || [check_effective_target_riscv_v] }]
> + || [check_effective_target_riscv_v]
> + || [check_effective_target_loongarch_sx] }]
> }
>
> # Return 1 if the target supports vector conditional operations, 0 otherwise.
> @@ -8826,7 +8899,9 @@ proc check_effective_target_vect_condition { } {
> && [check_effective_target_s390_vx])
> || [istarget amdgcn-*-*]
> || ([istarget riscv*-*-*]
> - && [check_effective_target_riscv_v]) }}]
> + && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx]) }}]
> }
>
> # Return 1 if the target supports vector conditional operations where
> @@ -8845,7 +8920,9 @@ proc check_effective_target_vect_cond_mixed { } {
> && [check_effective_target_s390_vx])
> || [istarget amdgcn-*-*]
> || ([istarget riscv*-*-*]
> - && [check_effective_target_riscv_v]) }}]
> + && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx]) }}]
> }
>
> # Return 1 if the target supports vector char multiplication, 0 otherwise.
> @@ -8863,7 +8940,9 @@ proc check_effective_target_vect_char_mult { } {
> && [check_effective_target_s390_vx])
> || [istarget amdgcn-*-*]
> || ([istarget riscv*-*-*]
> - && [check_effective_target_riscv_v]) }}]
> + && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx]) }}]
> }
>
> # Return 1 if the target supports vector short multiplication, 0 otherwise.
> @@ -8882,7 +8961,9 @@ proc check_effective_target_vect_short_mult { } {
> && [check_effective_target_s390_vx])
> || [istarget amdgcn-*-*]
> || ([istarget riscv*-*-*]
> - && [check_effective_target_riscv_v]) }}]
> + && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx]) }}]
> }
>
> # Return 1 if the target supports vector int multiplication, 0 otherwise.
> @@ -8900,7 +8981,9 @@ proc check_effective_target_vect_int_mult { } {
> && [check_effective_target_s390_vx])
> || [istarget amdgcn-*-*]
> || ([istarget riscv*-*-*]
> - && [check_effective_target_riscv_v]) }}]
> + && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx]) }}]
> }
>
> # Return 1 if the target supports 64 bit hardware vector
> @@ -8919,7 +9002,9 @@ proc check_effective_target_vect_long_mult { } {
> || ([istarget mips*-*-*]
> && [et-is-effective-target mips_msa])
> || ([istarget riscv*-*-*]
> - && [check_effective_target_riscv_v]) } {
> + && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx]) } {
> set answer 1
> } else {
> set answer 0
> @@ -8936,8 +9021,6 @@ proc check_effective_target_vect_int_mod { } {
> expr { ([istarget powerpc*-*-*]
> && [check_effective_target_has_arch_pwr10])
> || [istarget amdgcn-*-*]
> - || ([istarget loongarch*-*-*]
> - && [check_effective_target_loongarch_sx])
> || ([istarget riscv*-*-*]
> && [check_effective_target_riscv_v]) }}]
> }
> @@ -8957,7 +9040,9 @@ proc check_effective_target_vect_extract_even_odd { } {
> || ([istarget s390*-*-*]
> && [check_effective_target_s390_vx])
> || ([istarget riscv*-*-*]
> - && [check_effective_target_riscv_v]) }}]
> + && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx]) }}]
> }
>
> # Return 1 if the target supports vector interleaving, 0 otherwise.
> @@ -8975,7 +9060,9 @@ proc check_effective_target_vect_interleave { } {
> || ([istarget s390*-*-*]
> && [check_effective_target_s390_vx])
> || ([istarget riscv*-*-*]
> - && [check_effective_target_riscv_v]) }}]
> + && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx]) }}]
> }
>
> foreach N {2 3 4 5 6 7 8} {
> @@ -9100,7 +9187,9 @@ proc check_effective_target_vect_call_copysignf { } {
> || [istarget aarch64*-*-*]
> || [istarget amdgcn-*-*]
> || ([istarget riscv*-*-*]
> - && [check_effective_target_riscv_v]) }}]
> + && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx]) }}]
> }
>
> # Return 1 if the target supports hardware square root instructions.
> @@ -9139,7 +9228,9 @@ proc check_effective_target_vect_call_sqrtf { } {
> && [check_effective_target_s390_vx])
> || [istarget amdgcn-*-*]
> || ([istarget riscv*-*-*]
> - && [check_effective_target_riscv_v]) }}]
> + && [check_effective_target_riscv_v])
> + || ([istarget loongarch*-*-*]
> + && [check_effective_target_loongarch_sx]) }}]
> }
>
> # Return 1 if the target supports vector lrint calls.
> @@ -9148,7 +9239,8 @@ proc check_effective_target_vect_call_lrint { } {
> set et_vect_call_lrint 0
> if { (([istarget i?86-*-*] || [istarget x86_64-*-*])
> && [check_effective_target_ilp32])
> - || [istarget amdgcn-*-*] } {
> + || [istarget amdgcn-*-*]
> + || [istarget loongarch*-*-*] } {
> set et_vect_call_lrint 1
> }
>
> @@ -9161,7 +9253,8 @@ proc check_effective_target_vect_call_lrint { } {
> proc check_effective_target_vect_call_btrunc { } {
> return [check_cached_effective_target_indexed vect_call_btrunc {
> expr { [istarget aarch64*-*-*]
> - || [istarget amdgcn-*-*] }}]
> + || [istarget amdgcn-*-*]
> + || [istarget loongarch*-*-*] }}]
> }
>
> # Return 1 if the target supports vector btruncf calls.
> @@ -9169,7 +9262,8 @@ proc check_effective_target_vect_call_btrunc { } {
> proc check_effective_target_vect_call_btruncf { } {
> return [check_cached_effective_target_indexed vect_call_btruncf {
> expr { [istarget aarch64*-*-*]
> - || [istarget amdgcn-*-*] }}]
> + || [istarget amdgcn-*-*]
> + || [istarget loongarch*-*-*] }}]
> }
>
> # Return 1 if the target supports vector ceil calls.
> @@ -9177,7 +9271,8 @@ proc check_effective_target_vect_call_btruncf { } {
> proc check_effective_target_vect_call_ceil { } {
> return [check_cached_effective_target_indexed vect_call_ceil {
> expr { [istarget aarch64*-*-*]
> - || [istarget amdgcn-*-*] }}]
> + || [istarget amdgcn-*-*]
> + || [istarget loongarch*-*-*] }}]
> }
>
> # Return 1 if the target supports vector ceilf calls.
> @@ -9185,7 +9280,8 @@ proc check_effective_target_vect_call_ceil { } {
> proc check_effective_target_vect_call_ceilf { } {
> return [check_cached_effective_target_indexed vect_call_ceilf {
> expr { [istarget aarch64*-*-*]
> - || [istarget amdgcn-*-*] }}]
> + || [istarget amdgcn-*-*]
> + || [istarget loongarch*-*-*] }}]
> }
>
> # Return 1 if the target supports vector floor calls.
> @@ -9193,7 +9289,8 @@ proc check_effective_target_vect_call_ceilf { } {
> proc check_effective_target_vect_call_floor { } {
> return [check_cached_effective_target_indexed vect_call_floor {
> expr { [istarget aarch64*-*-*]
> - || [istarget amdgcn-*-*] }}]
> + || [istarget amdgcn-*-*]
> + || [istarget loongarch*-*-*] }}]
> }
>
> # Return 1 if the target supports vector floorf calls.
> @@ -9201,21 +9298,24 @@ proc check_effective_target_vect_call_floor { } {
> proc check_effective_target_vect_call_floorf { } {
> return [check_cached_effective_target_indexed vect_call_floorf {
> expr { [istarget aarch64*-*-*]
> - || [istarget amdgcn-*-*] }}]
> + || [istarget amdgcn-*-*]
> + || [istarget loongarch*-*-*] }}]
> }
>
> # Return 1 if the target supports vector lceil calls.
>
> proc check_effective_target_vect_call_lceil { } {
> return [check_cached_effective_target_indexed vect_call_lceil {
> - expr { [istarget aarch64*-*-*] }}]
> + expr { [istarget aarch64*-*-*]
> + || [istarget loongarch*-*-*] }}]
> }
>
> # Return 1 if the target supports vector lfloor calls.
>
> proc check_effective_target_vect_call_lfloor { } {
> return [check_cached_effective_target_indexed vect_call_lfloor {
> - expr { [istarget aarch64*-*-*] }}]
> + expr { [istarget aarch64*-*-*]
> + || [istarget loongarch*-*-*] }}]
> }
>
> # Return 1 if the target supports vector nearbyint calls.
> @@ -9252,6 +9352,7 @@ proc check_effective_target_vect_logical_reduc { } {
> return [expr { [check_effective_target_aarch64_sve]
> || [istarget amdgcn-*-*]
> || [check_effective_target_riscv_v]
> + || [check_effective_target_loongarch_sx]
> || [istarget i?86-*-*] || [istarget x86_64-*-*]}]
> }
>
> @@ -9269,7 +9370,8 @@ proc check_effective_target_section_anchors { } {
> return [check_cached_effective_target section_anchors {
> expr { [istarget powerpc*-*-*]
> || [istarget arm*-*-*]
> - || [istarget aarch64*-*-*] }}]
> + || [istarget aarch64*-*-*]
> + || [istarget loongarch*-*-*] }}]
> }
>
> # Return 1 if the target supports atomic operations on "int_128" values.
> @@ -11580,8 +11682,8 @@ proc check_vect_support_and_set_flags { } {
> set dg-do-what-default compile
> }
> } elseif [istarget loongarch*-*-*] {
> - lappend DEFAULT_VECTCFLAGS "-mdouble-float" "-mlasx"
> - if [check_effective_target_loongarch_asx_hw] {
> + lappend DEFAULT_VECTCFLAGS "-mdouble-float" "-mlsx"
> + if [check_effective_target_loongarch_sx_hw] {
> set dg-do-what-default run
> } else {
> set dg-do-what-default compile
> @@ -12147,7 +12249,8 @@ proc check_effective_target_builtin_eh_return { } {
>
> proc check_effective_target_vect_max_reduc { } {
> if { [istarget aarch64*-*-*] || [is-effective-target arm_neon]
> - || [check_effective_target_riscv_v] } {
> + || [check_effective_target_riscv_v]
> + || [check_effective_target_loongarch_sx] } {
> return 1
> }
> return 0
> @@ -13149,7 +13252,7 @@ proc check_effective_target_loongarch_sx { } {
> #if !defined(__loongarch_sx)
> #error "LSX not defined"
> #endif
> - }]
> + } "-mlsx"]
> }
>
> proc check_effective_target_loongarch_sx_hw { } {
> @@ -13169,7 +13272,7 @@ proc check_effective_target_loongarch_asx { } {
> #if !defined(__loongarch_asx)
> #error "LASX not defined"
> #endif
> - }]
> + } "-mlasx"]
> }
>
> proc check_effective_target_loongarch_asx_hw { } {
