On Tue, 19 Dec 2023, Juzhe-Zhong wrote:
> Due to recent VLSmode changes (Change for fixing ICE and run-time FAIL).
>
> The dump check is same as ARM SVE now. So adapt test for RISC-V.
OK.
> gcc/testsuite/ChangeLog:
>
> * gcc.dg/vect/bb-slp-cond-1.c: Adapt for RISC-V.
>
> ---
> gcc/testsuite/gcc.dg/vect/bb-slp-cond-1.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-cond-1.c
> b/gcc/testsuite/gcc.dg/vect/bb-slp-cond-1.c
> index 4089eb51b2e..8faf6b6e3ac 100644
> --- a/gcc/testsuite/gcc.dg/vect/bb-slp-cond-1.c
> +++ b/gcc/testsuite/gcc.dg/vect/bb-slp-cond-1.c
> @@ -47,6 +47,6 @@ int main ()
> }
>
> /* { dg-final { scan-tree-dump {(no need for alias check [^\n]* when VF is
> 1|no alias between [^\n]* when [^\n]* is outside \(-16, 16\))} "vect" {
> target vect_element_align } } } */
> -/* { dg-final { scan-tree-dump-times "loop vectorized" 1 "vect" { target {
> vect_element_align && { ! { amdgcn-*-* riscv*-*-* } } } } } } */
> -/* { dg-final { scan-tree-dump-times "loop vectorized" 2 "vect" { target {
> amdgcn-*-* riscv*-*-* } } } } */
> +/* { dg-final { scan-tree-dump-times "loop vectorized" 1 "vect" { target {
> vect_element_align && { ! { amdgcn-*-* } } } } } } */
> +/* { dg-final { scan-tree-dump-times "loop vectorized" 2 "vect" { target {
> amdgcn-*-* } } } } */
>
>
--
Richard Biener <rguent...@suse.de>
SUSE Software Solutions Germany GmbH,
Frankenstrasse 146, 90461 Nuernberg, Germany;
GF: Ivo Totev, Andrew McDonald, Werner Knoblich; (HRB 36809, AG Nuernberg)
