Hi!
The following testcase ICEs, because the signbit<mode>2 expander uses an
explicit SUBREG in the pattern around match_operand with register_operand
predicate. If we are unlucky enough that expansion tries to expand it
with some SUBREG as operands[1], we have two nested SUBREGs in the IL,
which is not valid and causes ICE later.
Fixed thusly, bootstrapped/regtested on x86_64-linux and i686-linux, ok
for trunk?
2023-12-04 Jakub Jelinek <ja...@redhat.com>
PR target/112816
* config/i386/sse.md (signbit<mode>2): Force operands[1] into a REG.
* gcc.target/i386/sse2-pr112816.c: New test.
--- gcc/config/i386/sse.md.jj 2023-12-01 08:10:42.311330174 +0100
+++ gcc/config/i386/sse.md 2023-12-02 09:53:45.489970487 +0100
@@ -5116,7 +5116,10 @@ (define_expand "signbit<mode>2"
(match_operand:VF1_AVX2 1 "register_operand") 0)
(match_dup 2)))]
"TARGET_SSE2"
- "operands[2] = GEN_INT (GET_MODE_UNIT_BITSIZE (<MODE>mode)-1);")
+{
+ operands[1] = force_reg (<MODE>mode, operands[1]);
+ operands[2] = GEN_INT (GET_MODE_UNIT_BITSIZE (<MODE>mode)-1);
+})
;; Also define scalar versions. These are used for abs, neg, and
;; conditional move. Using subregs into vector modes causes register
--- gcc/testsuite/gcc.target/i386/sse2-pr112816.c.jj 2023-12-02
10:00:23.623394880 +0100
+++ gcc/testsuite/gcc.target/i386/sse2-pr112816.c 2023-12-02
09:59:47.024909235 +0100
@@ -0,0 +1,16 @@
+/* PR target/112816 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+#define N 4
+struct S { float x[N]; };
+struct T { int x[N]; };
+
+struct T
+foo (struct S x)
+{
+ struct T res;
+ for (int i = 0; i < N; ++i)
+ res.x[i] = __builtin_signbit (x.x[i]) ? -1 : 0;
+ return res;
+}
Jakub
