Alex Coplan <alex.cop...@arm.com> writes: > Later patches in the series allow ldp and stp to use SVE modes if > -msve-vector-bits=128 is provided. This patch therefore adjusts tests > that pass -msve-vector-bits=128 to allow ldp/stp to save/restore SVE > registers. > > OK for trunk? > > gcc/testsuite/ChangeLog: > > * gcc.target/aarch64/sve/pcs/stack_clash_1_128.c: Allow ldp/stp saves > of SVE registers. > * gcc.target/aarch64/sve/pcs/struct_3_128.c: Likewise.
OK, thanks. Richard > --- > .../aarch64/sve/pcs/stack_clash_1_128.c | 32 +++++++++++++++++++ > .../gcc.target/aarch64/sve/pcs/struct_3_128.c | 29 +++++++++++++++++ > 2 files changed, 61 insertions(+) > > diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_128.c > b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_128.c > index 404301dc0c1..795429b01cb 100644 > --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_128.c > +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_128.c > @@ -19,6 +19,7 @@ > ** str p13, \[sp, #9, mul vl\] > ** str p14, \[sp, #10, mul vl\] > ** str p15, \[sp, #11, mul vl\] > +** ( > ** str z8, \[sp, #2, mul vl\] > ** str z9, \[sp, #3, mul vl\] > ** str z10, \[sp, #4, mul vl\] > @@ -35,7 +36,18 @@ > ** str z21, \[sp, #15, mul vl\] > ** str z22, \[sp, #16, mul vl\] > ** str z23, \[sp, #17, mul vl\] > +** | > +** stp q8, q9, \[sp, 32\] > +** stp q10, q11, \[sp, 64\] > +** stp q12, q13, \[sp, 96\] > +** stp q14, q15, \[sp, 128\] > +** stp q16, q17, \[sp, 160\] > +** stp q18, q19, \[sp, 192\] > +** stp q20, q21, \[sp, 224\] > +** stp q22, q23, \[sp, 256\] > +** ) > ** ptrue p0\.b, vl16 > +** ( > ** ldr z8, \[sp, #2, mul vl\] > ** ldr z9, \[sp, #3, mul vl\] > ** ldr z10, \[sp, #4, mul vl\] > @@ -52,6 +64,16 @@ > ** ldr z21, \[sp, #15, mul vl\] > ** ldr z22, \[sp, #16, mul vl\] > ** ldr z23, \[sp, #17, mul vl\] > +** | > +** ldp q8, q9, \[sp, 32\] > +** ldp q10, q11, \[sp, 64\] > +** ldp q12, q13, \[sp, 96\] > +** ldp q14, q15, \[sp, 128\] > +** ldp q16, q17, \[sp, 160\] > +** ldp q18, q19, \[sp, 192\] > +** ldp q20, q21, \[sp, 224\] > +** ldp q22, q23, \[sp, 256\] > +** ) > ** ldr p4, \[sp\] > ** ldr p5, \[sp, #1, mul vl\] > ** ldr p6, \[sp, #2, mul vl\] > @@ -101,16 +123,26 @@ test_2 (void) > ** str p5, \[sp\] > ** str p6, \[sp, #1, mul vl\] > ** str p11, \[sp, #2, mul vl\] > +** ( > ** str z8, \[sp, #1, mul vl\] > ** str z13, \[sp, #2, mul vl\] > ** str z19, \[sp, #3, mul vl\] > ** str z20, \[sp, #4, mul vl\] > +** | > +** stp q8, q13, \[sp, 16\] > +** stp q19, q20, \[sp, 48\] > +** ) > ** str z22, \[sp, #5, mul vl\] > ** ptrue p0\.b, vl16 > +** ( > ** ldr z8, \[sp, #1, mul vl\] > ** ldr z13, \[sp, #2, mul vl\] > ** ldr z19, \[sp, #3, mul vl\] > ** ldr z20, \[sp, #4, mul vl\] > +** | > +** ldp q8, q13, \[sp, 16\] > +** ldp q19, q20, \[sp, 48\] > +** ) > ** ldr z22, \[sp, #5, mul vl\] > ** ldr p5, \[sp\] > ** ldr p6, \[sp, #1, mul vl\] > diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/struct_3_128.c > b/gcc/testsuite/gcc.target/aarch64/sve/pcs/struct_3_128.c > index f6d78469aa5..0d330c015b9 100644 > --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/struct_3_128.c > +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/struct_3_128.c > @@ -220,6 +220,7 @@ SEL2 (struct, pst_arr5) > /* > ** test_pst_arr5: > ** sub sp, sp, #128 > +** ( > ** str z0, \[sp\] > ** str z1, \[sp, #1, mul vl\] > ** str z2, \[sp, #2, mul vl\] > @@ -228,6 +229,12 @@ SEL2 (struct, pst_arr5) > ** str z5, \[sp, #5, mul vl\] > ** str z6, \[sp, #6, mul vl\] > ** str z7, \[sp, #7, mul vl\] > +** | > +** stp q0, q1, \[sp\] > +** stp q2, q3, \[sp, 32\] > +** stp q4, q5, \[sp, 64\] > +** stp q6, q7, \[sp, 96\] > +** ) > ** mov (x7, sp|w7, wsp) > ** add sp, sp, #?128 > ** ret > @@ -374,8 +381,12 @@ SEL2 (struct, pst_uniform1) > /* > ** test_pst_uniform1: > ** sub sp, sp, #32 > +** ( > ** str z0, \[sp\] > ** str z1, \[sp, #1, mul vl\] > +** | > +** stp q0, q1, \[sp\] > +** ) > ** mov (x7, sp|w7, wsp) > ** add sp, sp, #?32 > ** ret > @@ -398,8 +409,12 @@ SEL2 (struct, pst_uniform2) > /* > ** test_pst_uniform2: > ** sub sp, sp, #48 > +** ( > ** str z0, \[sp\] > ** str z1, \[sp, #1, mul vl\] > +** | > +** stp q0, q1, \[sp\] > +** ) > ** str z2, \[sp, #2, mul vl\] > ** mov (x7, sp|w7, wsp) > ** add sp, sp, #?48 > @@ -424,10 +439,15 @@ SEL2 (struct, pst_uniform3) > /* > ** test_pst_uniform3: > ** sub sp, sp, #64 > +** ( > ** str z0, \[sp\] > ** str z1, \[sp, #1, mul vl\] > ** str z2, \[sp, #2, mul vl\] > ** str z3, \[sp, #3, mul vl\] > +** | > +** stp q0, q1, \[sp\] > +** stp q2, q3, \[sp, 32\] > +** ) > ** mov (x7, sp|w7, wsp) > ** add sp, sp, #?64 > ** ret > @@ -456,8 +476,12 @@ SEL2 (struct, pst_uniform4) > ** ptrue (p[0-7])\.b, vl16 > ** st1w z0\.s, \2, \[x7\] > ** add (x[0-9]+), x7, #?32 > +** ( > ** str z1, \[\3\] > ** str z2, \[\3, #1, mul vl\] > +** | > +** stp q1, q2, \[\3\] > +** ) > ** str z3, \[\3, #2, mul vl\] > ** st1w z4\.s, \2, \[x7, #6, mul vl\] > ** add sp, sp, #?144 > @@ -542,10 +566,15 @@ SEL2 (struct, pst_mixed2) > ** str p2, \[sp, #18, mul vl\] > ** add (x[0-9]+), sp, #?38 > ** st1b z2\.b, \1, \[\4\] > +** ( > ** str z3, \[sp, #4, mul vl\] > ** str z4, \[sp, #5, mul vl\] > ** str z5, \[sp, #6, mul vl\] > ** str z6, \[sp, #7, mul vl\] > +** | > +** stp q3, q4, \[sp, 64\] > +** stp q5, q6, \[sp, 96\] > +** ) > ** mov (x7, sp|w7, wsp) > ** add sp, sp, #?128 > ** ret
