LGTM
On Sun, Nov 19, 2023 at 1:36 PM Maciej W. Rozycki <ma...@embecosm.com> wrote:
>
> Verify, for short forward branch targets and the conditional-move
> operations that already work as expected, that if-conversion triggers
> via `noce_try_cmove' already at `-mbranch-cost=1' and that extraneous
> instructions such as SNEZ, etc. are not present in output. Cover all
> integer relational operations to make sure no corner case escapes.
>
> gcc/testsuite/
> * gcc.target/riscv/movdieq-sfb.c: New test.
> * gcc.target/riscv/movdige-sfb.c: New test.
> * gcc.target/riscv/movdigeu-sfb.c: New test.
> * gcc.target/riscv/movdigt-sfb.c: New test.
> * gcc.target/riscv/movdigtu-sfb.c: New test.
> * gcc.target/riscv/movdile-sfb.c: New test.
> * gcc.target/riscv/movdileu-sfb.c: New test.
> * gcc.target/riscv/movdilt-sfb.c: New test.
> * gcc.target/riscv/movdiltu-sfb.c: New test.
> * gcc.target/riscv/movdine-sfb.c: New test.
> * gcc.target/riscv/movsieq-sfb.c: New test.
> * gcc.target/riscv/movsige-sfb.c: New test.
> * gcc.target/riscv/movsigeu-sfb.c: New test.
> * gcc.target/riscv/movsigt-sfb.c: New test.
> * gcc.target/riscv/movsigtu-sfb.c: New test.
> * gcc.target/riscv/movsile-sfb.c: New test.
> * gcc.target/riscv/movsileu-sfb.c: New test.
> * gcc.target/riscv/movsilt-sfb.c: New test.
> * gcc.target/riscv/movsiltu-sfb.c: New test.
> * gcc.target/riscv/movsine-sfb.c: New test.
> ---
> gcc/testsuite/gcc.target/riscv/movdieq-sfb.c | 25
> +++++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movdige-sfb.c | 26
> ++++++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movdigeu-sfb.c | 26
> ++++++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movdigt-sfb.c | 26
> ++++++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movdigtu-sfb.c | 26
> ++++++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movdile-sfb.c | 26
> ++++++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movdileu-sfb.c | 26
> ++++++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movdilt-sfb.c | 26
> ++++++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movdiltu-sfb.c | 26
> ++++++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movdine-sfb.c | 25
> +++++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movsieq-sfb.c | 25
> +++++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movsige-sfb.c | 26
> ++++++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movsigeu-sfb.c | 26
> ++++++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movsigt-sfb.c | 26
> ++++++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movsigtu-sfb.c | 26
> ++++++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movsile-sfb.c | 26
> ++++++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movsileu-sfb.c | 26
> ++++++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movsilt-sfb.c | 26
> ++++++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movsiltu-sfb.c | 26
> ++++++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movsine-sfb.c | 25
> +++++++++++++++++++++++++
> 20 files changed, 516 insertions(+)
>
> gcc-riscv-test-movcc.diff
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdieq-sfb.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdieq-sfb.c
> @@ -0,0 +1,25 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
> +/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1
> -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdieq (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w == x ? y : z;
> +}
> +
> +/* Expect short forward branch assembly like:
> +
> + bne a0,a1,1f # movcc
> + mv a3,a2
> +1:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1
> "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through
> noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s\[^\\s\]+\\s#
> movcc\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdige-sfb.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdige-sfb.c
> @@ -0,0 +1,26 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
> +/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1
> -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdige (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w >= x ? y : z;
> +}
> +
> +/* Expect short forward branch assembly like:
> +
> + blt a0,a1,1f # movcc
> + mv a3,a2
> +1:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1
> "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through
> noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s\[^\\s\]+\\s#
> movcc\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdigeu-sfb.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdigeu-sfb.c
> @@ -0,0 +1,26 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
> +/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1
> -fdump-rtl-ce1" } */
> +
> +typedef unsigned int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdigeu (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w >= x ? y : z;
> +}
> +
> +/* Expect short forward branch assembly like:
> +
> + bltu a0,a1,1f # movcc
> + mv a3,a2
> +1:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1
> "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through
> noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times
> "\\s(?:bgeu|bgtu|bleu|bltu)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdigt-sfb.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdigt-sfb.c
> @@ -0,0 +1,26 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
> +/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1
> -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdigt (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w > x ? y : z;
> +}
> +
> +/* Expect short forward branch assembly like:
> +
> + ble a0,a1,1f # movcc
> + mv a3,a2
> +1:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1
> "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through
> noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s\[^\\s\]+\\s#
> movcc\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdigtu-sfb.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdigtu-sfb.c
> @@ -0,0 +1,26 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
> +/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1
> -fdump-rtl-ce1" } */
> +
> +typedef unsigned int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdigtu (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w > x ? y : z;
> +}
> +
> +/* Expect short forward branch assembly like:
> +
> + bleu a0,a1,1f # movcc
> + mv a3,a2
> +1:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1
> "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through
> noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times
> "\\s(?:bgeu|bgtu|bleu|bltu)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdile-sfb.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdile-sfb.c
> @@ -0,0 +1,26 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
> +/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1
> -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdile (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w <= x ? y : z;
> +}
> +
> +/* Expect short forward branch assembly like:
> +
> + bgt a0,a1,1f # movcc
> + mv a3,a2
> +1:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1
> "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through
> noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|bgt)\\s\[^\\s\]+\\s#
> movcc\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdileu-sfb.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdileu-sfb.c
> @@ -0,0 +1,26 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
> +/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1
> -fdump-rtl-ce1" } */
> +
> +typedef unsigned int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdileu (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w <= x ? y : z;
> +}
> +
> +/* Expect short forward branch assembly like:
> +
> + bgtu a0,a1,1f # movcc
> + mv a3,a2
> +1:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1
> "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through
> noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times
> "\\s(?:bgeu|bgtu|bleu|bltu)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdilt-sfb.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdilt-sfb.c
> @@ -0,0 +1,26 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
> +/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1
> -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdilt (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w < x ? y : z;
> +}
> +
> +/* Expect short forward branch assembly like:
> +
> + bge a0,a1,1f # movcc
> + mv a3,a2
> +1:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1
> "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through
> noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s\[^\\s\]+\\s#
> movcc\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdiltu-sfb.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdiltu-sfb.c
> @@ -0,0 +1,26 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
> +/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1
> -fdump-rtl-ce1" } */
> +
> +typedef unsigned int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdiltu (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w < x ? y : z;
> +}
> +
> +/* Expect short forward branch assembly like:
> +
> + bgeu a0,a1,1f # movcc
> + mv a3,a2
> +1:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1
> "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through
> noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times
> "\\s(?:bgeu|bgtu|bleu|bltu)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdine-sfb.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdine-sfb.c
> @@ -0,0 +1,25 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
> +/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1
> -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdine (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w != x ? y : z;
> +}
> +
> +/* Expect short forward branch assembly like:
> +
> + beq a0,a1,1f # movcc
> + mv a3,a2
> +1:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1
> "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through
> noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s\[^\\s\]+\\s#
> movcc\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsieq-sfb.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsieq-sfb.c
> @@ -0,0 +1,25 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
> +/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1
> -fdump-rtl-ce1" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc -mtune=sifive-7-series -mbranch-cost=1
> -fdump-rtl-ce1" { target { rv32 } } } */
> +
> +typedef int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsieq (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w == x ? y : z;
> +}
> +
> +/* Expect short forward branch assembly like:
> +
> + bne a0,a1,1f # movcc
> + mv a3,a2
> +1:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1
> "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through
> noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s\[^\\s\]+\\s#
> movcc\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsige-sfb.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsige-sfb.c
> @@ -0,0 +1,26 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
> +/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1
> -fdump-rtl-ce1" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc -mtune=sifive-7-series -mbranch-cost=1
> -fdump-rtl-ce1" { target { rv32 } } } */
> +
> +typedef int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsige (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w >= x ? y : z;
> +}
> +
> +/* Expect short forward branch assembly like:
> +
> + blt a0,a1,1f # movcc
> + mv a3,a2
> +1:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1
> "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through
> noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s\[^\\s\]+\\s#
> movcc\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsigeu-sfb.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsigeu-sfb.c
> @@ -0,0 +1,26 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
> +/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1
> -fdump-rtl-ce1" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc -mtune=sifive-7-series -mbranch-cost=1
> -fdump-rtl-ce1" { target { rv32 } } } */
> +
> +typedef unsigned int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsigeu (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w >= x ? y : z;
> +}
> +
> +/* Expect short forward branch assembly like:
> +
> + bltu a0,a1,1f # movcc
> + mv a3,a2
> +1:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1
> "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through
> noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times
> "\\s(?:bgeu|bgtu|bleu|bltu)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsigt-sfb.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsigt-sfb.c
> @@ -0,0 +1,26 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
> +/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1
> -fdump-rtl-ce1" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc -mtune=sifive-7-series -mbranch-cost=1
> -fdump-rtl-ce1" { target { rv32 } } } */
> +
> +typedef int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsigt (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w > x ? y : z;
> +}
> +
> +/* Expect short forward branch assembly like:
> +
> + ble a0,a1,1f # movcc
> + mv a3,a2
> +1:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1
> "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through
> noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bgt|ble)\\s\[^\\s\]+\\s#
> movcc\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsigtu-sfb.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsigtu-sfb.c
> @@ -0,0 +1,26 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
> +/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1
> -fdump-rtl-ce1" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc -mtune=sifive-7-series -mbranch-cost=1
> -fdump-rtl-ce1" { target { rv32 } } } */
> +
> +typedef unsigned int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsigtu (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w > x ? y : z;
> +}
> +
> +/* Expect short forward branch assembly like:
> +
> + bleu a0,a1,1f # movcc
> + mv a3,a2
> +1:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1
> "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through
> noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times
> "\\s(?:bgeu|bgtu|bleu|bltu)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsile-sfb.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsile-sfb.c
> @@ -0,0 +1,26 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
> +/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1
> -fdump-rtl-ce1" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc -mtune=sifive-7-series -mbranch-cost=1
> -fdump-rtl-ce1" { target { rv32 } } } */
> +
> +typedef int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsile (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w <= x ? y : z;
> +}
> +
> +/* Expect short forward branch assembly like:
> +
> + bgt a0,a1,1f # movcc
> + mv a3,a2
> +1:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1
> "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through
> noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s\[^\\s\]+\\s#
> movcc\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsileu-sfb.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsileu-sfb.c
> @@ -0,0 +1,26 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
> +/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1
> -fdump-rtl-ce1" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc -mtune=sifive-7-series -mbranch-cost=1
> -fdump-rtl-ce1" { target { rv32 } } } */
> +
> +typedef unsigned int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsileu (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w <= x ? y : z;
> +}
> +
> +/* Expect short forward branch assembly like:
> +
> + bgtu a0,a1,1f # movcc
> + mv a3,a2
> +1:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1
> "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through
> noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times
> "\\s(?:bgeu|bgtu|bleu|bltu)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsilt-sfb.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsilt-sfb.c
> @@ -0,0 +1,26 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
> +/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1
> -fdump-rtl-ce1" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc -mtune=sifive-7-series -mbranch-cost=1
> -fdump-rtl-ce1" { target { rv32 } } } */
> +
> +typedef int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsilt (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w < x ? y : z;
> +}
> +
> +/* Expect short forward branch assembly like:
> +
> + bge a0,a1,1f # movcc
> + mv a3,a2
> +1:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1
> "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through
> noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s\[^\\s\]+\\s#
> movcc\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsiltu-sfb.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsiltu-sfb.c
> @@ -0,0 +1,26 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
> +/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1
> -fdump-rtl-ce1" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc -mtune=sifive-7-series -mbranch-cost=1
> -fdump-rtl-ce1" { target { rv32 } } } */
> +
> +typedef unsigned int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsiltu (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w < x ? y : z;
> +}
> +
> +/* Expect short forward branch assembly like:
> +
> + bgeu a0,a1,1f # movcc
> + mv a3,a2
> +1:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1
> "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through
> noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times
> "\\s(?:bgeu|bgtu|bleu|bltu)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsine-sfb.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsine-sfb.c
> @@ -0,0 +1,25 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
> +/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1
> -fdump-rtl-ce1" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc -mtune=sifive-7-series -mbranch-cost=1
> -fdump-rtl-ce1" { target { rv32 } } } */
> +
> +typedef int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsine (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w != x ? y : z;
> +}
> +
> +/* Expect short forward branch assembly like:
> +
> + beq a0,a1,1f # movcc
> + mv a3,a2
> +1:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1
> "ce1" } } */
> +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through
> noce_try_cmove" 1 "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s\[^\\s\]+\\s#
> movcc\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
