On 10/20/23 03:53, Christoph Muellner wrote:
From: Christoph Müllner <christoph.muell...@vrull.eu>
This two patches add support for the XTheadMemIdx
and XTheadFMemIdx ISA extensions, that support additional
addressing modes. The extensions are implemented in a range
of T-Head cores (e.g. C906, C910, C920) and are available
on the market for quite some time.
The ISA spec can be found here:
https://github.com/T-head-Semi/thead-extension-spec
An initial version of these patches has been sent a while ago.
Jeff Law suggested to use INSNs instead of peepholes to let
the combiner do the optimization. This is the major change
that this patches have seen.
Did you happen to do any before/after testing? And if so, did using the
combiner help with discovery of these cases? I would expect it to have
done so, but it's always nice to have a confirmation.
If not, no big deal from a review standpoint. Given I looked at these
before, I'll take this small kit again.
Jeff
