The normal form of a CONST_INT which represents an integer of a mode
with fewer bits than in HOST_WIDE_INT is sign extended. This even holds
for unsigned integers.
This fixes an ICE during cse1 where we bail out at rtl.h:2297 since
INTVAL (x.first) == sext_hwi (INTVAL (x.first), precision) does not hold.
gcc/ChangeLog:
* config/s390/vector.md (popcountv8hi2_vx): Sign extend each
unsigned vector element.
---
gcc/config/s390/vector.md | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index f0e9ed3d263..7d1eb36e844 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -1154,14 +1154,14 @@
(plus:V16QI (match_dup 2) (match_dup 3)))
; Generate mask for the odd numbered byte elements
(set (match_dup 3)
- (const_vector:V16QI [(const_int 0) (const_int 255)
- (const_int 0) (const_int 255)
- (const_int 0) (const_int 255)
- (const_int 0) (const_int 255)
- (const_int 0) (const_int 255)
- (const_int 0) (const_int 255)
- (const_int 0) (const_int 255)
- (const_int 0) (const_int 255)]))
+ (const_vector:V16QI [(const_int 0) (const_int -1)
+ (const_int 0) (const_int -1)
+ (const_int 0) (const_int -1)
+ (const_int 0) (const_int -1)
+ (const_int 0) (const_int -1)
+ (const_int 0) (const_int -1)
+ (const_int 0) (const_int -1)
+ (const_int 0) (const_int -1)]))
; Zero out the even indexed bytes
(set (match_operand:V8HI 0 "register_operand" "=v")
(and:V8HI (subreg:V8HI (match_dup 2) 0)
--
2.41.0
