From: Kong Lingling <lingling.k...@intel.com>
Extend GENERAL_REGS with extra r16-r31 registers like REX registers,
named as REX2 registers. They will only be enabled under
TARGET_APX_EGPR.
gcc/ChangeLog:
* config/i386/i386-protos.h (x86_extended_rex2reg_mentioned_p):
New function prototype.
* config/i386/i386.cc (regclass_map): Add mapping for 16 new
general registers.
(debugger64_register_map): Likewise.
(ix86_conditional_register_usage): Clear REX2 register when APX
disabled.
(ix86_code_end): Add handling for REX2 reg.
(print_reg): Likewise.
(ix86_output_jmp_thunk_or_indirect): Likewise.
(ix86_output_indirect_branch_via_reg): Likewise.
(ix86_attr_length_vex_default): Likewise.
(ix86_emit_save_regs): Adjust to allow saving r31.
(ix86_register_priority): Set REX2 reg priority same as REX.
(x86_extended_reg_mentioned_p): Add check for REX2 regs.
(x86_extended_rex2reg_mentioned_p): New function.
* config/i386/i386.h (CALL_USED_REGISTERS): Add new extended
registers.
(REG_ALLOC_ORDER): Likewise.
(FIRST_REX2_INT_REG): Define.
(LAST_REX2_INT_REG): Ditto.
(GENERAL_REGS): Add 16 new registers.
(INT_SSE_REGS): Likewise.
(FLOAT_INT_REGS): Likewise.
(FLOAT_INT_SSE_REGS): Likewise.
(INT_MASK_REGS): Likewise.
(ALL_REGS):Likewise.
(REX2_INT_REG_P): Define.
(REX2_INT_REGNO_P): Ditto.
(GENERAL_REGNO_P): Add REX2_INT_REGNO_P.
(REGNO_OK_FOR_INDEX_P): Ditto.
(REG_OK_FOR_INDEX_NONSTRICT_P): Add new extended registers.
* config/i386/i386.md: Add 16 new integer general
registers.
gcc/testsuite/ChangeLog:
* gcc.target/i386/apx-egprs-names.c: New test.
* gcc.target/i386/apx-spill_to_egprs-1.c: Likewise.
* gcc.target/i386/apx-interrupt-1.c: Likewise.
Co-authored-by: Hongyu Wang <hongyu.w...@intel.com>
Co-authored-by: Hongtao Liu <hongtao....@intel.com>
---
gcc/config/i386/i386-protos.h | 1 +
gcc/config/i386/i386.cc | 67 ++++++++++--
gcc/config/i386/i386.h | 46 +++++---
gcc/config/i386/i386.md | 18 +++-
.../gcc.target/i386/apx-egprs-names.c | 17 +++
.../gcc.target/i386/apx-interrupt-1.c | 102 ++++++++++++++++++
.../gcc.target/i386/apx-spill_to_egprs-1.c | 25 +++++
7 files changed, 252 insertions(+), 24 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/i386/apx-egprs-names.c
create mode 100644 gcc/testsuite/gcc.target/i386/apx-interrupt-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/apx-spill_to_egprs-1.c
diff --git a/gcc/config/i386/i386-protos.h b/gcc/config/i386/i386-protos.h
index 9ffb125fc2b..bd4782800c4 100644
--- a/gcc/config/i386/i386-protos.h
+++ b/gcc/config/i386/i386-protos.h
@@ -64,6 +64,7 @@ extern bool symbolic_reference_mentioned_p (rtx);
extern bool extended_reg_mentioned_p (rtx);
extern bool x86_extended_QIreg_mentioned_p (rtx_insn *);
extern bool x86_extended_reg_mentioned_p (rtx);
+extern bool x86_extended_rex2reg_mentioned_p (rtx);
extern bool x86_maybe_negate_const_int (rtx *, machine_mode);
extern machine_mode ix86_cc_mode (enum rtx_code, rtx, rtx);
diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc
index 477e6cecc38..fb1672f0b3d 100644
--- a/gcc/config/i386/i386.cc
+++ b/gcc/config/i386/i386.cc
@@ -169,7 +169,12 @@ enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
ALL_SSE_REGS, ALL_SSE_REGS, ALL_SSE_REGS, ALL_SSE_REGS,
/* Mask registers. */
ALL_MASK_REGS, MASK_REGS, MASK_REGS, MASK_REGS,
- MASK_REGS, MASK_REGS, MASK_REGS, MASK_REGS
+ MASK_REGS, MASK_REGS, MASK_REGS, MASK_REGS,
+ /* REX2 registers */
+ GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
+ GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
+ GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
+ GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
};
/* The "default" register map used in 32bit mode. */
@@ -227,7 +232,10 @@ int const debugger64_register_map[FIRST_PSEUDO_REGISTER] =
/* AVX-512 registers 24-31 */
75, 76, 77, 78, 79, 80, 81, 82,
/* Mask registers */
- 118, 119, 120, 121, 122, 123, 124, 125
+ 118, 119, 120, 121, 122, 123, 124, 125,
+ /* rex2 extend interger registers */
+ 130, 131, 132, 133, 134, 135, 136, 137,
+ 138, 139, 140, 141, 142, 143, 144, 145
};
/* Define the register numbers to be used in Dwarf debugging information.
@@ -521,6 +529,13 @@ ix86_conditional_register_usage (void)
accessible_reg_set &= ~reg_class_contents[ALL_MASK_REGS];
}
+
+ /* If APX is disabled, disable the registers. */
+ if (! (TARGET_APX_EGPR && TARGET_64BIT))
+ {
+ for (i = FIRST_REX2_INT_REG; i <= LAST_REX2_INT_REG; i++)
+ CLEAR_HARD_REG_BIT (accessible_reg_set, i);
+ }
}
/* Canonicalize a comparison from one we don't have to one we do have. */
@@ -6188,6 +6203,13 @@ ix86_code_end (void)
regno, false);
}
+ for (regno = FIRST_REX2_INT_REG; regno <= LAST_REX2_INT_REG; regno++)
+ {
+ if (TEST_HARD_REG_BIT (indirect_thunks_used, regno))
+ output_indirect_thunk_function (indirect_thunk_prefix_none,
+ regno, false);
+ }
+
for (regno = FIRST_INT_REG; regno <= LAST_INT_REG; regno++)
{
char name[32];
@@ -7199,10 +7221,10 @@ choose_baseaddr (HOST_WIDE_INT cfa_offset, unsigned int
*align,
static void
ix86_emit_save_regs (void)
{
- unsigned int regno;
+ int regno;
rtx_insn *insn;
- for (regno = FIRST_PSEUDO_REGISTER - 1; regno-- > 0; )
+ for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--)
if (GENERAL_REGNO_P (regno) && ix86_save_reg (regno, true, true))
{
insn = emit_insn (gen_push (gen_rtx_REG (word_mode, regno)));
@@ -13046,7 +13068,7 @@ print_reg (rtx x, int code, FILE *file)
/* Irritatingly, AMD extended registers use
different naming convention: "r%d[bwd]" */
- if (REX_INT_REGNO_P (regno))
+ if (REX_INT_REGNO_P (regno) || REX2_INT_REGNO_P (regno))
{
gcc_assert (TARGET_64BIT);
switch (msize)
@@ -16260,7 +16282,7 @@ ix86_output_jmp_thunk_or_indirect (const char
*thunk_name, const int regno)
{
if (thunk_name != NULL)
{
- if (REX_INT_REGNO_P (regno)
+ if ((REX_INT_REGNO_P (regno) || REX2_INT_REGNO_P (regno))
&& ix86_indirect_branch_cs_prefix)
fprintf (asm_out_file, "\tcs\n");
fprintf (asm_out_file, "\tjmp\t");
@@ -16312,7 +16334,7 @@ ix86_output_indirect_branch_via_reg (rtx call_op, bool
sibcall_p)
{
if (thunk_name != NULL)
{
- if (REX_INT_REGNO_P (regno)
+ if ((REX_INT_REGNO_P (regno) || REX_INT_REGNO_P (regno))
&& ix86_indirect_branch_cs_prefix)
fprintf (asm_out_file, "\tcs\n");
fprintf (asm_out_file, "\tcall\t");
@@ -17069,19 +17091,26 @@ ix86_attr_length_vex_default (rtx_insn *insn, bool
has_0f_opcode,
for (i = recog_data.n_operands - 1; i >= 0; --i)
if (REG_P (recog_data.operand[i]))
{
- /* REX.W bit uses 3 byte VEX prefix. */
+ /* REX.W bit uses 3 byte VEX prefix.
+ REX2 with vex use extended EVEX prefix length is 4-byte. */
if (GET_MODE (recog_data.operand[i]) == DImode
&& GENERAL_REG_P (recog_data.operand[i]))
return 3 + 1;
/* REX.B bit requires 3-byte VEX. Right here we don't know which
- operand will be encoded using VEX.B, so be conservative. */
+ operand will be encoded using VEX.B, so be conservative.
+ REX2 with vex use extended EVEX prefix length is 4-byte. */
if (REX_INT_REGNO_P (recog_data.operand[i])
+ || REX2_INT_REGNO_P (recog_data.operand[i])
|| REX_SSE_REGNO_P (recog_data.operand[i]))
reg_only = 3 + 1;
}
else if (MEM_P (recog_data.operand[i]))
{
+ /* REX2.X or REX2.B bits use 3 byte VEX prefix. */
+ if (x86_extended_rex2reg_mentioned_p (recog_data.operand[i]))
+ return 4;
+
/* REX.X or REX.B bits use 3 byte VEX prefix. */
if (x86_extended_reg_mentioned_p (recog_data.operand[i]))
return 3 + 1;
@@ -19518,6 +19547,8 @@ ix86_register_priority (int hard_regno)
/* New x86-64 int registers result in bigger code size. Discourage them. */
if (REX_INT_REGNO_P (hard_regno))
return 2;
+ if (REX2_INT_REGNO_P (hard_regno))
+ return 2;
/* New x86-64 SSE registers result in bigger code size. Discourage them. */
if (REX_SSE_REGNO_P (hard_regno))
return 2;
@@ -22764,7 +22795,23 @@ x86_extended_reg_mentioned_p (rtx insn)
{
const_rtx x = *iter;
if (REG_P (x)
- && (REX_INT_REGNO_P (REGNO (x)) || REX_SSE_REGNO_P (REGNO (x))))
+ && (REX_INT_REGNO_P (REGNO (x)) || REX_SSE_REGNO_P (REGNO (x))
+ || REX2_INT_REGNO_P (REGNO (x))))
+ return true;
+ }
+ return false;
+}
+
+/* Return true when INSN mentions register that must be encoded using REX2
+ prefix. */
+bool
+x86_extended_rex2reg_mentioned_p (rtx insn)
+{
+ subrtx_iterator::array_type array;
+ FOR_EACH_SUBRTX (iter, array, INSN_P (insn) ? PATTERN (insn) : insn,
NONCONST)
+ {
+ const_rtx x = *iter;
+ if (REG_P (x) && REX2_INT_REGNO_P (REGNO (x)))
return true;
}
return false;
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 8c7ed541a8f..215f6b8db55 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -948,7 +948,11 @@ extern const char *host_detect_local_cpu (int argc, const
char **argv);
/*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \
0, 0, 0, 0, 0, 0, 0, 0, \
/* k0, k1, k2, k3, k4, k5, k6, k7*/ \
- 0, 0, 0, 0, 0, 0, 0, 0 }
+ 0, 0, 0, 0, 0, 0, 0, 0, \
+/* r16, r17, r18, r19, r20, r21, r22, r23*/ \
+ 0, 0, 0, 0, 0, 0, 0, 0, \
+/* r24, r25, r26, r27, r28, r29, r30, r31*/ \
+ 0, 0, 0, 0, 0, 0, 0, 0} \
/* 1 for registers not available across function calls.
These must include the FIXED_REGISTERS and also any
@@ -985,7 +989,11 @@ extern const char *host_detect_local_cpu (int argc, const
char **argv);
/*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \
1, 1, 1, 1, 1, 1, 1, 1, \
/* k0, k1, k2, k3, k4, k5, k6, k7*/ \
- 1, 1, 1, 1, 1, 1, 1, 1 }
+ 1, 1, 1, 1, 1, 1, 1, 1, \
+/* r16, r17, r18, r19, r20, r21, r22, r23*/ \
+ 1, 1, 1, 1, 1, 1, 1, 1, \
+/* r24, r25, r26, r27, r28, r29, r30, r31*/ \
+ 1, 1, 1, 1, 1, 1, 1, 1} \
/* Order in which to allocate registers. Each register must be
listed once, even those in FIXED_REGISTERS. List frame pointer
@@ -1001,7 +1009,8 @@ extern const char *host_detect_local_cpu (int argc, const
char **argv);
16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
- 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 }
+ 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
+ 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91}
/* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
to be rearranged based on a particular function. When using sse math,
@@ -1203,6 +1212,9 @@ extern const char *host_detect_local_cpu (int argc, const
char **argv);
#define FIRST_MASK_REG MASK0_REG
#define LAST_MASK_REG MASK7_REG
+#define FIRST_REX2_INT_REG R16_REG
+#define LAST_REX2_INT_REG R31_REG
+
/* Override this in other tm.h files to cope with various OS lossage
requiring a frame pointer. */
#ifndef SUBTARGET_FRAME_POINTER_REQUIRED
@@ -1280,7 +1292,9 @@ enum reg_class
INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp
%esp
- %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */
+ %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15
+ %r16 %r17 %r18 %r19 %r20 %r21 %r22 %r23
+ %r24 %r25 %r26 %r27 %r28 %r29 %r30 %r31 */
FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
FLOAT_REGS,
SSE_FIRST_REG,
@@ -1380,7 +1394,7 @@ enum reg_class
{ 0x7e, 0xff0, 0x0 }, /* TLS_GOTBASE_REGS */ \
{ 0x7f, 0xff0, 0x0 }, /* INDEX_REGS */ \
{ 0x900ff, 0x0, 0x0 }, /* LEGACY_REGS */ \
- { 0x900ff, 0xff0, 0x0 }, /* GENERAL_REGS */ \
+ { 0x900ff, 0xff0, 0xffff000 }, /* GENERAL_REGS */
\
{ 0x100, 0x0, 0x0 }, /* FP_TOP_REG */ \
{ 0x200, 0x0, 0x0 }, /* FP_SECOND_REG */ \
{ 0xff00, 0x0, 0x0 }, /* FLOAT_REGS */ \
@@ -1390,13 +1404,13 @@ enum reg_class
{ 0xff00000, 0xfffff000, 0xf }, /* ALL_SSE_REGS */ \
{ 0xf0000000, 0xf, 0x0 }, /* MMX_REGS */ \
{ 0xff0ff00, 0xfffff000, 0xf }, /* FLOAT_SSE_REGS */ \
- { 0x9ffff, 0xff0, 0x0 }, /* FLOAT_INT_REGS */ \
- { 0xff900ff, 0xfffffff0, 0xf }, /* INT_SSE_REGS */ \
- { 0xff9ffff, 0xfffffff0, 0xf }, /* FLOAT_INT_SSE_REGS */ \
+ { 0x9ffff, 0xff0, 0xffff000 }, /* FLOAT_INT_REGS */
\
+ { 0xff900ff, 0xfffffff0, 0xffff00f }, /* INT_SSE_REGS */
\
+ { 0xff9ffff, 0xfffffff0, 0xffff00f }, /* FLOAT_INT_SSE_REGS */
\
{ 0x0, 0x0, 0xfe0 }, /* MASK_REGS */ \
{ 0x0, 0x0, 0xff0 }, /* ALL_MASK_REGS */ \
- { 0x900ff, 0xff0, 0xff0 }, /* INT_MASK_REGS */ \
-{ 0xffffffff, 0xffffffff, 0xfff } /* ALL_REGS */ \
+ { 0x900ff, 0xff0, 0xffffff0 }, /* INT_MASK_REGS */ \
+{ 0xffffffff, 0xffffffff, 0xfffffff } /* ALL_REGS */ \
}
/* The same information, inverted:
@@ -1426,13 +1440,17 @@ enum reg_class
#define REX_INT_REGNO_P(N) \
IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG)
+#define REX2_INT_REG_P(X) (REG_P (X) && REX2_INT_REGNO_P (REGNO (X)))
+#define REX2_INT_REGNO_P(N) \
+ IN_RANGE ((N), FIRST_REX2_INT_REG, LAST_REX2_INT_REG)
+
#define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
#define GENERAL_REGNO_P(N) \
- (LEGACY_INT_REGNO_P (N) || REX_INT_REGNO_P (N))
+ (LEGACY_INT_REGNO_P (N) || REX_INT_REGNO_P (N) || REX2_INT_REGNO_P (N))
#define INDEX_REG_P(X) (REG_P (X) && INDEX_REGNO_P (REGNO (X)))
#define INDEX_REGNO_P(N) \
- (LEGACY_INDEX_REGNO_P (N) || REX_INT_REGNO_P (N))
+ (LEGACY_INDEX_REGNO_P (N) || REX_INT_REGNO_P (N) || REX2_INT_REGNO_P (N))
#define ANY_QI_REG_P(X) (REG_P (X) && ANY_QI_REGNO_P (REGNO (X)))
#define ANY_QI_REGNO_P(N) \
@@ -1990,7 +2008,9 @@ do {
\
"xmm20", "xmm21", "xmm22", "xmm23", \
"xmm24", "xmm25", "xmm26", "xmm27", \
"xmm28", "xmm29", "xmm30", "xmm31", \
- "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" }
+ "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", \
+ "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
+ "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" }
#define REGISTER_NAMES HI_REGISTER_NAMES
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index eef8a0e01eb..e3270658cb7 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -464,7 +464,23 @@ (define_constants
(MASK5_REG 73)
(MASK6_REG 74)
(MASK7_REG 75)
- (FIRST_PSEUDO_REG 76)
+ (R16_REG 76)
+ (R17_REG 77)
+ (R18_REG 78)
+ (R19_REG 79)
+ (R20_REG 80)
+ (R21_REG 81)
+ (R22_REG 82)
+ (R23_REG 83)
+ (R24_REG 84)
+ (R25_REG 85)
+ (R26_REG 86)
+ (R27_REG 87)
+ (R28_REG 88)
+ (R29_REG 89)
+ (R30_REG 90)
+ (R31_REG 91)
+ (FIRST_PSEUDO_REG 92)
])
;; Insn callee abi index.
diff --git a/gcc/testsuite/gcc.target/i386/apx-egprs-names.c
b/gcc/testsuite/gcc.target/i386/apx-egprs-names.c
new file mode 100644
index 00000000000..445bcf2c250
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/apx-egprs-names.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mapxf -m64" } */
+/* { dg-final { scan-assembler "r31" } } */
+/* { dg-final { scan-assembler "r30" } } */
+/* { dg-final { scan-assembler "r29" } } */
+/* { dg-final { scan-assembler "r28" } } */
+void foo ()
+{
+ register long a __asm ("r31");
+ register int b __asm ("r30");
+ register short c __asm ("r29");
+ register char d __asm ("r28");
+ __asm__ __volatile__ ("mov %0, %%rax" : : "r" (a) : "rax");
+ __asm__ __volatile__ ("mov %0, %%eax" : : "r" (b) : "eax");
+ __asm__ __volatile__ ("mov %0, %%eax" : : "r" (c) : "eax");
+ __asm__ __volatile__ ("mov %0, %%eax" : : "r" (d) : "eax");
+}
diff --git a/gcc/testsuite/gcc.target/i386/apx-interrupt-1.c
b/gcc/testsuite/gcc.target/i386/apx-interrupt-1.c
new file mode 100644
index 00000000000..441dbf04bf2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/apx-interrupt-1.c
@@ -0,0 +1,102 @@
+/* { dg-do compile } */
+/* { dg-options "-mapxf -m64 -O2 -mgeneral-regs-only -mno-cld -mno-push-args
-maccumulate-outgoing-args" } */
+
+extern void foo (void *) __attribute__ ((interrupt));
+extern int bar (int);
+
+void foo (void *frame)
+{
+ int a,b,c,d,e,f,i;
+ a = bar (5);
+ b = bar (a);
+ c = bar (b);
+ d = bar (c);
+ e = bar (d);
+ f = bar (e);
+ for (i = 1; i < 10; i++)
+ {
+ a += bar (a + i) + bar (b + i) +
+ bar (c + i) + bar (d + i) +
+ bar (e + i) + bar (f + i);
+ }
+}
+/* { dg-final { scan-assembler-times "push(?:l|q)\[\\t \]*%(?:e|r)ax" 1 } } */
+/* { dg-final { scan-assembler-times "push(?:l|q)\[\\t \]*%(?:e|r)bx" 1 } } */
+/* { dg-final { scan-assembler-times "push(?:l|q)\[\\t \]*%(?:e|r)cx" 1 } } */
+/* { dg-final { scan-assembler-times "push(?:l|q)\[\\t \]*%(?:e|r)dx" 1 } } */
+/* { dg-final { scan-assembler-times "push(?:l|q)\[\\t \]*%(?:e|r)si" 1 } } */
+/* { dg-final { scan-assembler-times "pushq\[\\t \]*%rdi" 1 { target { ! ia32
} } } } */
+/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r8" 1 { target { ! ia32 }
} } } */
+/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r9" 1 { target { ! ia32 }
} } } */
+/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r10" 1 { target { ! ia32
} } } } */
+/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r11" 1 { target { ! ia32
} } } } */
+/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r12" 1 { target { ! ia32
} } } } */
+/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r13" 1 { target { ! ia32
} } } } */
+/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r14" 1 { target { ! ia32
} } } } */
+/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r15" 1 { target { ! ia32
} } } } */
+/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r16" 1 { target { ! ia32
} } } } */
+/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r17" 1 { target { ! ia32
} } } } */
+/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r18" 1 { target { ! ia32
} } } } */
+/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r19" 1 { target { ! ia32
} } } } */
+/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r20" 1 { target { ! ia32
} } } } */
+/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r21" 1 { target { ! ia32
} } } } */
+/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r22" 1 { target { ! ia32
} } } } */
+/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r23" 1 { target { ! ia32
} } } } */
+/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r24" 1 { target { ! ia32
} } } } */
+/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r25" 1 { target { ! ia32
} } } } */
+/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r26" 1 { target { ! ia32
} } } } */
+/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r27" 1 { target { ! ia32
} } } } */
+/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r28" 1 { target { ! ia32
} } } } */
+/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r29" 1 { target { ! ia32
} } } } */
+/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r30" 1 { target { ! ia32
} } } } */
+/* { dg-final { scan-assembler-times "pushq\[\\t \]*%r31" 1 { target { ! ia32
} } } } */
+/* { dg-final { scan-assembler-times {\t\.cfi_offset 145, -16} 1 } } */
+/* { dg-final { scan-assembler-times {\t\.cfi_offset 144, -24} 1 } } */
+/* { dg-final { scan-assembler-times {\t\.cfi_offset 143, -32} 1 } } */
+/* { dg-final { scan-assembler-times {\t\.cfi_offset 142, -40} 1 } } */
+/* { dg-final { scan-assembler-times {\t\.cfi_offset 141, -48} 1 } } */
+/* { dg-final { scan-assembler-times {\t\.cfi_offset 140, -56} 1 } } */
+/* { dg-final { scan-assembler-times {\t\.cfi_offset 139, -64} 1 } } */
+/* { dg-final { scan-assembler-times {\t\.cfi_offset 138, -72} 1 } } */
+/* { dg-final { scan-assembler-times {\t\.cfi_offset 137, -80} 1 } } */
+/* { dg-final { scan-assembler-times {\t\.cfi_offset 136, -88} 1 } } */
+/* { dg-final { scan-assembler-times {\t\.cfi_offset 135, -96} 1 } } */
+/* { dg-final { scan-assembler-times {\t\.cfi_offset 134, -104} 1 } } */
+/* { dg-final { scan-assembler-times {\t\.cfi_offset 133, -112} 1 } } */
+/* { dg-final { scan-assembler-times {\t\.cfi_offset 132, -120} 1 } } */
+/* { dg-final { scan-assembler-times {\t\.cfi_offset 131, -128} 1 } } */
+/* { dg-final { scan-assembler-times {\t\.cfi_offset 130, -136} 1 } } */
+/* { dg-final { scan-assembler-times ".cfi_restore" 15} } */
+/* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)ax" 1 } } */
+/* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)bx" 1 } } */
+/* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)cx" 1 } } */
+/* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)dx" 1 } } */
+/* { dg-final { scan-assembler-times "pop(?:l|q)\[\\t \]*%(?:e|r)si" 1 } } */
+/* { dg-final { scan-assembler-times "popq\[\\t \]*%rdi" 1 { target { ! ia32 }
} } } */
+/* { dg-final { scan-assembler-times "popq\[\\t \]*%r8" 1 { target { ! ia32 }
} } } */
+/* { dg-final { scan-assembler-times "popq\[\\t \]*%r9" 1 { target { ! ia32 }
} } } */
+/* { dg-final { scan-assembler-times "popq\[\\t \]*%r10" 1 { target { ! ia32 }
} } } */
+/* { dg-final { scan-assembler-times "popq\[\\t \]*%r11" 1 { target { ! ia32 }
} } } */
+/* { dg-final { scan-assembler-times "popq\[\\t \]*%r12" 1 { target { ! ia32 }
} } } */
+/* { dg-final { scan-assembler-times "popq\[\\t \]*%r13" 1 { target { ! ia32 }
} } } */
+/* { dg-final { scan-assembler-times "popq\[\\t \]*%r14" 1 { target { ! ia32 }
} } } */
+/* { dg-final { scan-assembler-times "popq\[\\t \]*%r15" 1 { target { ! ia32 }
} } } */
+/* { dg-final { scan-assembler-times "popq\[\\t \]*%r16" 1 { target { ! ia32 }
} } } */
+/* { dg-final { scan-assembler-times "popq\[\\t \]*%r17" 1 { target { ! ia32 }
} } } */
+/* { dg-final { scan-assembler-times "popq\[\\t \]*%r18" 1 { target { ! ia32 }
} } } */
+/* { dg-final { scan-assembler-times "popq\[\\t \]*%r19" 1 { target { ! ia32 }
} } } */
+/* { dg-final { scan-assembler-times "popq\[\\t \]*%r20" 1 { target { ! ia32 }
} } } */
+/* { dg-final { scan-assembler-times "popq\[\\t \]*%r21" 1 { target { ! ia32 }
} } } */
+/* { dg-final { scan-assembler-times "popq\[\\t \]*%r22" 1 { target { ! ia32 }
} } } */
+/* { dg-final { scan-assembler-times "popq\[\\t \]*%r23" 1 { target { ! ia32 }
} } } */
+/* { dg-final { scan-assembler-times "popq\[\\t \]*%r24" 1 { target { ! ia32 }
} } } */
+/* { dg-final { scan-assembler-times "popq\[\\t \]*%r25" 1 { target { ! ia32 }
} } } */
+/* { dg-final { scan-assembler-times "popq\[\\t \]*%r26" 1 { target { ! ia32 }
} } } */
+/* { dg-final { scan-assembler-times "popq\[\\t \]*%r27" 1 { target { ! ia32 }
} } } */
+/* { dg-final { scan-assembler-times "popq\[\\t \]*%r28" 1 { target { ! ia32 }
} } } */
+/* { dg-final { scan-assembler-times "popq\[\\t \]*%r29" 1 { target { ! ia32 }
} } } */
+/* { dg-final { scan-assembler-times "popq\[\\t \]*%r30" 1 { target { ! ia32 }
} } } */
+/* { dg-final { scan-assembler-times "popq\[\\t \]*%r31" 1 { target { ! ia32 }
} } } */
+/* { dg-final { scan-assembler-times "iret" 1 { target ia32 } } } */
+/* { dg-final { scan-assembler-times "iretq" 1 { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler-times "\tcld" 1 } } */
diff --git a/gcc/testsuite/gcc.target/i386/apx-spill_to_egprs-1.c
b/gcc/testsuite/gcc.target/i386/apx-spill_to_egprs-1.c
new file mode 100644
index 00000000000..290863d63a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/apx-spill_to_egprs-1.c
@@ -0,0 +1,25 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -march=skylake-avx512 -mapxf -DDTYPE32" } */
+
+#include "spill_to_mask-1.c"
+
+/* { dg-final { scan-assembler "movl\[ \t]+\[^\\n\\r\]*, %r16d" } } */
+/* { dg-final { scan-assembler "movl\[ \t]+\[^\\n\\r\]*, %r17d" } } */
+/* { dg-final { scan-assembler "movl\[ \t]+\[^\\n\\r\]*, %r18d" } } */
+/* { dg-final { scan-assembler "movq\[ \t]+\[^\\n\\r\]*, %r19" } } */
+/* { dg-final { scan-assembler "movl\[ \t]+\[^\\n\\r\]*, %r20d" } } */
+/* { dg-final { scan-assembler "movl\[ \t]+\[^\\n\\r\]*, %r21d" } } */
+/* { dg-final { scan-assembler "movl\[ \t]+\[^\\n\\r\]*, %r22d" } } */
+/* { dg-final { scan-assembler "movl\[ \t]+\[^\\n\\r\]*, %r23d" } } */
+/* { dg-final { scan-assembler "movl\[ \t]+\[^\\n\\r\]*, %r24d" } } */
+/* { dg-final { scan-assembler "addl\[ \t]+\[^\\n\\r\]*, %r25d" } } */
+/* { dg-final { scan-assembler "movl\[ \t]+\[^\\n\\r\]*, %r26d" } } */
+/* { dg-final { scan-assembler "movl\[ \t]+\[^\\n\\r\]*, %r27d" } } */
+/* { dg-final { scan-assembler "movbel\[ \t]+\[^\\n\\r\]*, %r28d" } } */
+/* { dg-final { scan-assembler "movbel\[ \t]+\[^\\n\\r\]*, %r29d" } } */
+/* { dg-final { scan-assembler "movbel\[ \t]+\[^\\n\\r\]*, %r30d" } } */
+/* { dg-final { scan-assembler "movbel\[ \t]+\[^\\n\\r\]*, %r31d" } } */
+/* { dg-final { scan-assembler-not "knot" } } */
+/* { dg-final { scan-assembler-not "kxor" } } */
+/* { dg-final { scan-assembler-not "kor" } } */
+/* { dg-final { scan-assembler-not "kandn" } } */
--
2.31.1
