Hello,
As I explained earlier:
<https://gcc.gnu.org/pipermail/gcc-patches/2023-August/626916.html>,
the builtin function for RISC-V "__builtin_riscv_zicbop_cbo_prefetchi" is
completely broken. Instead, this patch set (in PATCH 1/2) creates three
new, working builtin intrinsics.
void __builtin_riscv_prefetch_i(void *addr, [intptr_t offset,] ...);
void __builtin_riscv_prefetch_r(void *addr, [intptr_t offset,] ...);
void __builtin_riscv_prefetch_w(void *addr, [intptr_t offset,] ...);
For consistency with "prefetch.i" and the reason I describe later (which
requires native instructions for "prefetch.r" and "prefetch.w"), I decided
to make builtin functions for "prefetch.[rw]" as well.
Optional second argument (named "offset" here) defaults to zero and must be
a compile-time integral constant. Also, it must be a valid offset for a
"prefetch.[irw]" HINT instruction (x % 32 == 0 && x >= -2048 && x < 2048).
They are defined if the 'Zicbop' extension is supported and expands to:
> prefetch.i offset(addr_reg) ; __builtin_riscv_prefetch_i
> prefetch.r offset(addr_reg) ; __builtin_riscv_prefetch_r
> prefetch.w offset(addr_reg) ; __builtin_riscv_prefetch_w
The hardest part of this patch set was to support builtin function with
variable argument (making "offset" optional). It required:
1. Support for variable argument function prototype for RISC-V builtins
(corresponding "..." on C-based languages)
2. Support for (non-vector) RISC-V builtins with custom expansion
(on RVV intrinsics, custom expansion is already implemented)
... and PATCH 2/2 fixes an ICE while I'm investigating regular prefetch
builtin (__builtin_prefetch). If the 'Zicbop' extension is enabled,
__builtin_prefetch with the first argument NULL or (not all but) some
fixed addresses (like ((void*)0x20)) can cause an ICE. This is because
the "r" constraint is not checked and a constant can be a first argument
of target-specific "prefetch" RTL instruction.
PATCH 2/2 fixes this issue by:
1. Making "prefetch" not an instruction but instead an expansion
(this is not rare; e.g. on i386) and
2. Coercing the address argument into a register in the expansion
It requires separate instructions for "prefetch.[rw]" and I decided to make
those prefetch instructions very similar to "prefetch.i". That's one of the
reasons I created builtins corresponding those.
Sincerely,
Tsukasa
Tsukasa OI (2):
RISC-V: Define not broken prefetch builtins
RISC-V: Fix ICE by expansion and register coercion
gcc/config/riscv/riscv-builtins.cc | 112 +++++++++++++++++-
gcc/config/riscv/riscv-cmo.def | 8 +-
gcc/config/riscv/riscv-ftypes.def | 1 +
gcc/config/riscv/riscv.md | 67 ++++++++---
gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c | 41 ++++---
gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c | 33 ++----
gcc/testsuite/gcc.target/riscv/cmo-zicbop-3.c | 29 +++++
gcc/testsuite/gcc.target/riscv/cmo-zicbop-4.c | 14 +++
gcc/testsuite/gcc.target/riscv/cmo-zicbop-5.c | 14 +++
gcc/testsuite/gcc.target/riscv/cmo-zicbop-6.c | 38 ++++++
.../gcc.target/riscv/cmo-zicbop-by-common-1.c | 17 +++
.../gcc.target/riscv/cmo-zicbop-by-common-2.c | 7 ++
.../gcc.target/riscv/cmo-zicbop-by-common-3.c | 13 ++
.../riscv/cmo-zicbop-by-common-ice-1.c | 13 ++
.../riscv/cmo-zicbop-by-common-ice-2.c | 7 ++
15 files changed, 350 insertions(+), 64 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-by-common-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-by-common-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-by-common-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-by-common-ice-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-by-common-ice-2.c
base-commit: 40ac613627205dd4d24ae136917e48b357fee758
--
2.42.0
