This patch makes cond autovec testcase checks more restrict.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c:
Assert of the number of vmerge.
* gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c: New test.
---
.../riscv/rvv/autovec/cond/cond_arith-1.c | 1 +
.../riscv/rvv/autovec/cond/cond_arith-10.c | 63 +++++++++++++++++++
.../riscv/rvv/autovec/cond/cond_arith-11.c | 31 +++++++++
.../riscv/rvv/autovec/cond/cond_arith-2.c | 1 +
.../riscv/rvv/autovec/cond/cond_arith-3.c | 1 +
.../riscv/rvv/autovec/cond/cond_arith-4.c | 1 +
.../riscv/rvv/autovec/cond/cond_arith-5.c | 1 +
.../riscv/rvv/autovec/cond/cond_arith-6.c | 1 +
.../riscv/rvv/autovec/cond/cond_arith-7.c | 1 +
.../riscv/rvv/autovec/cond/cond_arith-8.c | 1 +
.../rvv/autovec/cond/cond_arith_run-10.c | 34 ++++++++++
.../rvv/autovec/cond/cond_arith_run-11.c | 4 ++
.../cond/cond_convert_float2float-rv32-1.c | 1 +
.../cond/cond_convert_float2float-rv32-2.c | 1 +
.../cond/cond_convert_float2float-rv64-1.c | 1 +
.../cond/cond_convert_float2float-rv64-2.c | 1 +
.../cond/cond_convert_float2int-rv32-1.c | 1 +
.../cond/cond_convert_float2int-rv32-2.c | 1 +
.../cond/cond_convert_float2int-rv64-1.c | 1 +
.../cond/cond_convert_float2int-rv64-2.c | 1 +
.../cond/cond_convert_int2float-rv32-1.c | 1 +
.../cond/cond_convert_int2float-rv32-2.c | 1 +
.../cond/cond_convert_int2float-rv64-1.c | 1 +
.../cond/cond_convert_int2float-rv64-2.c | 1 +
.../cond/cond_convert_int2int-rv32-1.c | 2 +-
.../cond/cond_convert_int2int-rv32-2.c | 1 +
.../cond/cond_convert_int2int-rv64-1.c | 1 +
.../cond/cond_convert_int2int-rv64-2.c | 1 +
.../rvv/autovec/cond/cond_copysign-rv32gcv.c | 1 +
.../rvv/autovec/cond/cond_copysign-rv64gcv.c | 1 +
.../riscv/rvv/autovec/cond/cond_fadd-1.c | 1 +
.../riscv/rvv/autovec/cond/cond_fadd-2.c | 1 +
.../riscv/rvv/autovec/cond/cond_fadd-3.c | 1 +
.../riscv/rvv/autovec/cond/cond_fadd-4.c | 1 +
.../riscv/rvv/autovec/cond/cond_fma_fnma-1.c | 1 +
.../riscv/rvv/autovec/cond/cond_fma_fnma-2.c | 1 +
.../riscv/rvv/autovec/cond/cond_fma_fnma-3.c | 1 +
.../riscv/rvv/autovec/cond/cond_fma_fnma-4.c | 1 +
.../riscv/rvv/autovec/cond/cond_fma_fnma-5.c | 39 ++++++------
.../riscv/rvv/autovec/cond/cond_fma_fnma-6.c | 2 +
.../riscv/rvv/autovec/cond/cond_fma_fnma-7.c | 1 +
.../riscv/rvv/autovec/cond/cond_fma_fnma-8.c | 1 +
.../rvv/autovec/cond/cond_fma_fnma_run-5.c | 38 +++++------
.../riscv/rvv/autovec/cond/cond_fmax-1.c | 1 +
.../riscv/rvv/autovec/cond/cond_fmax-2.c | 1 +
.../riscv/rvv/autovec/cond/cond_fmax-3.c | 1 +
.../riscv/rvv/autovec/cond/cond_fmax-4.c | 1 +
.../riscv/rvv/autovec/cond/cond_fmin-1.c | 2 +-
.../riscv/rvv/autovec/cond/cond_fmin-2.c | 1 +
.../riscv/rvv/autovec/cond/cond_fmin-3.c | 1 +
.../riscv/rvv/autovec/cond/cond_fmin-4.c | 1 +
.../riscv/rvv/autovec/cond/cond_fms_fnms-1.c | 1 +
.../riscv/rvv/autovec/cond/cond_fms_fnms-2.c | 1 +
.../riscv/rvv/autovec/cond/cond_fms_fnms-3.c | 1 +
.../riscv/rvv/autovec/cond/cond_fms_fnms-4.c | 2 +
.../riscv/rvv/autovec/cond/cond_fms_fnms-5.c | 2 +
.../riscv/rvv/autovec/cond/cond_fms_fnms-6.c | 2 +
.../riscv/rvv/autovec/cond/cond_fmul-1.c | 1 +
.../riscv/rvv/autovec/cond/cond_fmul-2.c | 1 +
.../riscv/rvv/autovec/cond/cond_fmul-3.c | 1 +
.../riscv/rvv/autovec/cond/cond_fmul-4.c | 1 +
.../riscv/rvv/autovec/cond/cond_fmul-5.c | 29 +++++++++
.../riscv/rvv/autovec/cond/cond_fmul_run-5.c | 33 ++++++++++
.../rvv/autovec/cond/cond_logical_min_max-1.c | 1 +
.../rvv/autovec/cond/cond_logical_min_max-2.c | 1 +
.../rvv/autovec/cond/cond_logical_min_max-3.c | 1 +
.../rvv/autovec/cond/cond_logical_min_max-4.c | 1 +
.../rvv/autovec/cond/cond_logical_min_max-5.c | 1 +
.../riscv/rvv/autovec/cond/cond_shift-1.c | 1 +
.../riscv/rvv/autovec/cond/cond_shift-2.c | 1 +
.../riscv/rvv/autovec/cond/cond_shift-3.c | 1 +
.../riscv/rvv/autovec/cond/cond_shift-4.c | 1 +
.../riscv/rvv/autovec/cond/cond_shift-5.c | 1 +
.../riscv/rvv/autovec/cond/cond_shift-6.c | 1 +
.../riscv/rvv/autovec/cond/cond_shift-7.c | 1 +
.../riscv/rvv/autovec/cond/cond_shift-8.c | 1 +
.../riscv/rvv/autovec/cond/cond_shift-9.c | 1 +
.../riscv/rvv/autovec/cond/cond_sqrt-1.c | 1 +
.../riscv/rvv/autovec/cond/cond_sqrt-2.c | 1 +
.../riscv/rvv/autovec/cond/cond_unary-1.c | 2 +
.../riscv/rvv/autovec/cond/cond_unary-2.c | 2 +
.../riscv/rvv/autovec/cond/cond_unary-3.c | 2 +
.../riscv/rvv/autovec/cond/cond_unary-4.c | 2 +
.../riscv/rvv/autovec/cond/cond_unary-5.c | 2 +
.../riscv/rvv/autovec/cond/cond_unary-6.c | 2 +
.../riscv/rvv/autovec/cond/cond_unary-7.c | 2 +
.../riscv/rvv/autovec/cond/cond_unary-8.c | 2 +
87 files changed, 324 insertions(+), 40 deletions(-)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c
index 922be4d7d34..485c8f44580 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c
@@ -59,3 +59,4 @@ TEST_ALL
/* { dg-final { scan-assembler-times
{vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
/* { dg-final { scan-assembler-times
{vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
/* { dg-final { scan-assembler-times
{vfdiv\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c
new file mode 100644
index 00000000000..c96966a40bc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c
@@ -0,0 +1,63 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d
--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math
-fdump-tree-optimized-details" } */
+
+#include <stdint-gcc.h>
+
+#define TEST(TYPE, NAME, OP)
\
+ void __attribute__ ((noinline, noclone))
\
+ test_##TYPE##_##NAME (TYPE *__restrict x, TYPE *__restrict y,
\
+ TYPE *__restrict z, TYPE *__restrict pred, \
+ TYPE *__restrict merged, int n) \
+ {
\
+ for (int i = 0; i < n; ++i)
\
+ x[i] = pred[i] != 1 ? y[i] OP z[i] : merged[i];
\
+ }
+
+#define TEST_TYPE(TYPE)
\
+ TEST (TYPE, add, +)
\
+ TEST (TYPE, sub, -)
\
+ TEST (TYPE, mul, *)
\
+ TEST (TYPE, div, /)
+
+#define TEST_TYPE2(TYPE) TEST (TYPE, rem, %)
+
+#define TEST_ALL
\
+ TEST_TYPE (int8_t)
\
+ TEST_TYPE (uint8_t)
\
+ TEST_TYPE (int16_t)
\
+ TEST_TYPE (uint16_t)
\
+ TEST_TYPE (int32_t)
\
+ TEST_TYPE (uint32_t)
\
+ TEST_TYPE (int64_t)
\
+ TEST_TYPE (uint64_t)
\
+ TEST_TYPE2 (int8_t)
\
+ TEST_TYPE2 (uint8_t)
\
+ TEST_TYPE2 (int16_t)
\
+ TEST_TYPE2 (uint16_t)
\
+ TEST_TYPE2 (int32_t)
\
+ TEST_TYPE2 (uint32_t)
\
+ TEST_TYPE2 (int64_t)
\
+ TEST_TYPE2 (uint64_t)
\
+ TEST_TYPE (_Float16)
\
+ TEST_TYPE (float)
\
+ TEST_TYPE (double)
+
+TEST_ALL
+
+/* { dg-final { scan-tree-dump-times "\.COND_LEN_DIV" 8 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_LEN_MOD" 8 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_ADD" 11 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_SUB" 11 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_MUL" 11 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_RDIV" 3 "optimized" } } */
+/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t}
8 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t}
8 } } */
+/* { dg-final { scan-assembler-times {vmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t}
8 } } */
+/* { dg-final { scan-assembler-times
{vdivu?\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */
+/* { dg-final { scan-assembler-times {vrem\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t}
4 } } */
+/* { dg-final { scan-assembler-times
{vremu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-times
{vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-times
{vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-times
{vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-times
{vfdiv\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c
new file mode 100644
index 00000000000..40f636c3275
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d
--param=riscv-autovec-preference=scalable -fno-vect-cost-model
-fdump-tree-optimized-details" } */
+
+#include "cond_arith-1.c"
+
+/* { dg-final { scan-tree-dump-times "\.COND_LEN_DIV" 8 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_LEN_MOD" 8 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_LEN_RDIV" 3 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_ADD" 8 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_SUB" 8 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_MUL" 8 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_ADD" 8 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_SUB" 8 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_MUL" 8 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_LEN_ADD" 3 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_LEN_SUB" 3 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_LEN_MUL" 3 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_LEN_ADD" 3 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_LEN_SUB" 3 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_LEN_MUL" 3 "optimized" } } */
+/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t}
8 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t}
8 } } */
+/* { dg-final { scan-assembler-times {vmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t}
8 } } */
+/* { dg-final { scan-assembler-times
{vdivu?\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */
+/* { dg-final { scan-assembler-times {vrem\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t}
4 } } */
+/* { dg-final { scan-assembler-times
{vremu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-times
{vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-times
{vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-times
{vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-times
{vfdiv\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c
index 986a70e4507..40f636c3275 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c
@@ -28,3 +28,4 @@
/* { dg-final { scan-assembler-times
{vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
/* { dg-final { scan-assembler-times
{vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
/* { dg-final { scan-assembler-times
{vfdiv\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c
index a97d34facd8..ec5943c49ce 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c
@@ -68,3 +68,4 @@ TEST_ALL
/* { dg-final { scan-assembler-times
{vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */
/* { dg-final { scan-assembler-times
{vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */
/* { dg-final { scan-assembler-times
{vfdiv\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c
index 30089b784b9..abd91e75b65 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c
@@ -22,3 +22,4 @@
/* { dg-final { scan-assembler-times
{vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */
/* { dg-final { scan-assembler-times
{vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */
/* { dg-final { scan-assembler-times
{vfdiv\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c
index 2f9e883ff25..a47c295e06d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c
@@ -59,3 +59,4 @@ TEST_ALL
/* { dg-final { scan-assembler-times
{vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
/* { dg-final { scan-assembler-times
{vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
/* { dg-final { scan-assembler-times
{vfdiv\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c
index 13a230cca4f..2205862493a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c
@@ -28,3 +28,4 @@
/* { dg-final { scan-assembler-times
{vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
/* { dg-final { scan-assembler-times
{vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
/* { dg-final { scan-assembler-times
{vfdiv\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c
index e43f040cd1a..e02aeba31dc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c
@@ -57,3 +57,4 @@ TEST_ALL
/* { dg-final { scan-assembler-times
{vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
/* { dg-final { scan-assembler-times
{vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
/* { dg-final { scan-assembler-times
{vfdiv\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c
index eac77e08b75..3bff8df4a8e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c
@@ -77,3 +77,4 @@ TEST_ALL
/* { dg-final { scan-assembler-times
{vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 22 } } */
/* { dg-final { scan-assembler-times
{vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 22 } } */
/* { dg-final { scan-assembler-times
{vfdiv\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 22 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c
new file mode 100644
index 00000000000..343c77c69c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c
@@ -0,0 +1,34 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable
-fno-vect-cost-model -ffast-math" } */
+
+#include "cond_arith-10.c"
+
+#define N 99
+
+#undef TEST
+#define TEST(TYPE, NAME, OP)
\
+ {
\
+ TYPE x[N], y[N], z[N], pred[N], merged[N];
\
+ for (int i = 0; i < N; ++i)
\
+ {
\
+ y[i] = i * i; \
+ z[i] = ((i + 2) % 3) * (i + 1); \
+ pred[i] = i % 3; \
+ merged[i] = i; \
+ }
\
+ test_##TYPE##_##NAME (x, y, z, pred, merged, N);
\
+ for (int i = 0; i < N; ++i)
\
+ {
\
+ TYPE expected = i % 3 != 1 ? y[i] OP z[i] : merged[i]; \
+ if (x[i] != expected) \
+ __builtin_abort (); \
+ asm volatile ("" ::: "memory"); \
+ }
\
+ }
+
+int
+main (void)
+{
+ TEST_ALL
+ return 0;
+}
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c
new file mode 100644
index 00000000000..35435a3fe04
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable
-fno-vect-cost-model" } */
+
+#include "cond_arith_run-10.c"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c
index bb4873befda..4b8a75d2b2c 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c
@@ -9,3 +9,4 @@
/* { dg-final { scan-assembler-times
{\tvfncvt\.rod\.f\.f\.w\tv[0-9]+,v[0-9]+\n} 1 } } */
/* { dg-final { scan-assembler
{\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c
index 4ec20e5ff23..0a2aa7b2835 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c
@@ -9,3 +9,4 @@
/* { dg-final { scan-assembler-times
{\tvfncvt\.rod\.f\.f\.w\tv[0-9]+,v[0-9]+\n} 1 } } */
/* { dg-final { scan-assembler
{\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c
index ec861fe1658..7c9e6baebc0 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c
@@ -9,3 +9,4 @@
/* { dg-final { scan-assembler-times
{\tvfncvt\.rod\.f\.f\.w\tv[0-9]+,v[0-9]+\n} 1 } } */
/* { dg-final { scan-assembler
{\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c
index 455a4b36953..bdf9ad997a1 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c
@@ -9,3 +9,4 @@
/* { dg-final { scan-assembler-times
{\tvfncvt\.rod\.f\.f\.w\tv[0-9]+,v[0-9]+\n} 1 } } */
/* { dg-final { scan-assembler
{\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c
index 9dcbaa9b0a2..d3fe0c9b9ba 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c
@@ -15,3 +15,4 @@
/* { dg-final { scan-assembler-times
{\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+\n} 6 } } */
/* { dg-final { scan-assembler
{\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c
index 25d54247fed..d5ceda6ee9c 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c
@@ -15,3 +15,4 @@
/* { dg-final { scan-assembler-times
{\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+\n} 6 } } */
/* { dg-final { scan-assembler
{\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c
index 495f4b56a4d..23a9b138299 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c
@@ -15,3 +15,4 @@
/* { dg-final { scan-assembler-times
{\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+\n} 6 } } */
/* { dg-final { scan-assembler
{\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c
index 520c9df2dfb..c798e15b446 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c
@@ -15,3 +15,4 @@
/* { dg-final { scan-assembler-times
{\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+\n} 6 } } */
/* { dg-final { scan-assembler
{\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c
index f5d3bb4c789..857190d1575 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c
@@ -13,3 +13,4 @@
/* { dg-final { scan-assembler-times
{\tvfncvt\.f\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
/* { dg-final { scan-assembler
{\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c
index f5d3bb4c789..857190d1575 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c
@@ -13,3 +13,4 @@
/* { dg-final { scan-assembler-times
{\tvfncvt\.f\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
/* { dg-final { scan-assembler
{\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c
index 5ebed2f7fdc..169bc2338a9 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c
@@ -13,3 +13,4 @@
/* { dg-final { scan-assembler-times
{\tvfncvt\.f\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
/* { dg-final { scan-assembler
{\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c
index 097e377f107..c7021bea0f5 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c
@@ -13,3 +13,4 @@
/* { dg-final { scan-assembler-times
{\tvfncvt\.f\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
/* { dg-final { scan-assembler
{\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c
index 8c07e427560..9287abafabd 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c
@@ -14,4 +14,4 @@
/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+\n} 8 }
} */
/* { dg-final { scan-assembler
{\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
-
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c
index 74490cdc055..5c54eaefaeb 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c
@@ -14,3 +14,4 @@
/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+\n} 8 }
} */
/* { dg-final { scan-assembler
{\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c
index 00357966ba6..603395ff0b8 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c
@@ -14,3 +14,4 @@
/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+\n} 8 }
} */
/* { dg-final { scan-assembler
{\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c
index 3c4ad9c4f66..fbf5c0cabd4 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c
@@ -14,3 +14,4 @@
/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+\n} 8 }
} */
/* { dg-final { scan-assembler
{\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c
index cef531b9700..89b4e9a66f6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c
@@ -10,3 +10,4 @@
/* { dg-final { scan-assembler-times {\tvfsgnjx\.vv} 6 { xfail riscv*-*-* } }
} */
/* { dg-final { scan-assembler-times {\tvfsgnjn\.vv} 6 } } */
/* { dg-final { scan-assembler-not {\tvmerge\.vvm} } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c
index cc2aa4de757..5c559e68d5e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c
@@ -10,3 +10,4 @@
/* { dg-final { scan-assembler-times {\tvfsgnjx\.vv} 6 { xfail riscv*-*-* } }
} */
/* { dg-final { scan-assembler-times {\tvfsgnjn\.vv} 6 } } */
/* { dg-final { scan-assembler-not {\tvmerge\.vvm} } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c
index c9d14f27e5d..6342aaa7b40 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c
@@ -30,3 +30,4 @@
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times
{vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 18 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c
index 21f9f9f9107..d55d2c65e88 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c
@@ -29,3 +29,4 @@
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times
{vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 12 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c
index f71dbaa80ed..d33809f52fe 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c
@@ -30,3 +30,4 @@
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times
{vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 18 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c
index ffbe9a47cd9..2d754ffd17d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c
@@ -30,3 +30,4 @@
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times
{vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 18 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c
index 0b19c54b562..ca1b9d7a375 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c
@@ -33,3 +33,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times
{vnmsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
/* { dg-final { scan-assembler-times
{vfmadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
/* { dg-final { scan-assembler-times
{vfnmsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c
index bd61c0e2edc..dedae59744f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c
@@ -33,3 +33,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times
{vnmsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
/* { dg-final { scan-assembler-times
{vfmadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
/* { dg-final { scan-assembler-times
{vfnmsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c
index c011a290908..138819c56db 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c
@@ -33,3 +33,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times
{vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
/* { dg-final { scan-assembler-times
{vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
/* { dg-final { scan-assembler-times
{vfnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c
index 98ba3c1a58d..a84cb7b48c6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c
@@ -33,3 +33,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times
{vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
/* { dg-final { scan-assembler-times
{vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
/* { dg-final { scan-assembler-times
{vfnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvmerge\.vvm\t} 14 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c
index 98ba3c1a58d..0fc959ed543 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c
@@ -1,30 +1,29 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d
--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d
--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
-#define DEF_LOOP(TYPE, NAME, OP) \
- void __attribute__ ((noipa)) \
- test_##TYPE##_##NAME (TYPE *__restrict r, \
- TYPE *__restrict a, \
- TYPE *__restrict b, TYPE c, \
- TYPE *__restrict pred, int n) \
- { \
- for (int i = 0; i < n; ++i) \
- r[i] = pred[i] == 1 ? a[i] OP b[i] * c : pred[i]; \
+#define DEF_LOOP(TYPE, NAME, OP)
\
+ void __attribute__ ((noipa))
\
+ test_##TYPE##_##NAME (TYPE *__restrict r, TYPE *__restrict a,
\
+ TYPE *__restrict b, TYPE c, TYPE *__restrict pred, \
+ TYPE *__restrict merged, int n) \
+ {
\
+ for (int i = 0; i < n; ++i)
\
+ r[i] = pred[i] == 1 ? a[i] OP b[i] * c : merged[i];
\
}
-#define TEST_TYPE(T, TYPE) \
- T (TYPE, add, +) \
+#define TEST_TYPE(T, TYPE)
\
+ T (TYPE, add, +)
\
T (TYPE, sub, -)
-#define TEST_ALL(T) \
- TEST_TYPE (T, uint8_t) \
- TEST_TYPE (T, uint16_t) \
- TEST_TYPE (T, uint32_t) \
- TEST_TYPE (T, uint64_t) \
- TEST_TYPE (T, _Float16) \
- TEST_TYPE (T, float) \
+#define TEST_ALL(T)
\
+ TEST_TYPE (T, uint8_t)
\
+ TEST_TYPE (T, uint16_t)
\
+ TEST_TYPE (T, uint32_t)
\
+ TEST_TYPE (T, uint64_t)
\
+ TEST_TYPE (T, _Float16)
\
+ TEST_TYPE (T, float)
\
TEST_TYPE (T, double)
TEST_ALL (DEF_LOOP)
@@ -33,3 +32,5 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times
{vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
/* { dg-final { scan-assembler-times
{vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
/* { dg-final { scan-assembler-times
{vfnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* NOTE: 14 vmerge is need for other purpose. */
+/* { dg-final { scan-assembler-times {\tvmerge\.vvm\t} 14 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c
index e72eb5e7603..247b785c6f4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c
@@ -33,3 +33,5 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times
{vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
/* { dg-final { scan-assembler-times
{vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
/* { dg-final { scan-assembler-times
{vfnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* NOTE: 14 vmerge is need for other purpose. */
+/* { dg-final { scan-assembler-times {\tvmerge\.vvm\t} 14 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c
index 3a69a59e8e8..146f0e569aa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c
@@ -33,3 +33,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times
{vmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 12 } } */
/* { dg-final { scan-assembler-times
{vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 12 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c
index 4df9da8ea4e..619d7b9ed91 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c
@@ -33,3 +33,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times
{vmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 12 } } */
/* { dg-final { scan-assembler-times
{vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 12 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c
index 2aa25245669..c79ea5f610e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c
@@ -6,25 +6,25 @@
#define FACTOR 17
#define N 99
-#define TEST_LOOP(TYPE, NAME, OP) \
- { \
- TYPE r[N], a[N], b[N], pred[N]; \
- for (int i = 0; i < N; ++i) \
- { \
- a[i] = (i & 1 ? i : 3 * i); \
- b[i] = (i >> 4) << (i & 15); \
- pred[i] = i % 3 < i % 5; \
- asm volatile ("" ::: "memory"); \
- } \
- test_##TYPE##_##NAME (r, a, b, FACTOR, pred, N); \
- for (int i = 0; i < N; ++i) \
- { \
- TYPE expected \
- = pred[i] ? a[i] OP b[i] * (TYPE) FACTOR : 0; \
- if (r[i] != expected) \
- __builtin_abort (); \
- asm volatile ("" ::: "memory"); \
- } \
+#define TEST_LOOP(TYPE, NAME, OP)
\
+ {
\
+ TYPE r[N], a[N], b[N], pred[N], merged[N];
\
+ for (int i = 0; i < N; ++i)
\
+ {
\
+ a[i] = (i & 1 ? i : 3 * i); \
+ b[i] = (i >> 4) << (i & 15); \
+ pred[i] = i % 3 < i % 5; \
+ merged[i] = i * 5; \
+ asm volatile ("" ::: "memory"); \
+ }
\
+ test_##TYPE##_##NAME (r, a, b, FACTOR, pred, merged, N);
\
+ for (int i = 0; i < N; ++i)
\
+ {
\
+ TYPE expected = pred[i] ? a[i] OP b[i] * (TYPE) FACTOR : merged[i]; \
+ if (r[i] != expected) \
+ __builtin_abort (); \
+ asm volatile ("" ::: "memory"); \
+ }
\
}
int
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c
index fe37794afeb..5cc56f635b2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c
@@ -31,3 +31,4 @@
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times
{vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c
index f25562b22dd..18c232b2d1c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c
@@ -30,3 +30,4 @@
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times
{vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c
index a23f4916caa..491188ede4e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c
@@ -31,3 +31,4 @@
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times
{vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c
index 79e4771eaf3..c915e937b16 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c
@@ -31,3 +31,4 @@
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times
{vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c
index f1596409312..3670ee7060f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c
@@ -7,4 +7,4 @@
#include "cond_fmax-1.c"
/* { dg-final { scan-assembler-times
{vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
-
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c
index 7c8c79ee251..caf38002a54 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c
@@ -7,3 +7,4 @@
#include "cond_fmax-2.c"
/* { dg-final { scan-assembler-times
{vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c
index aee0e3572b0..1df320581d3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c
@@ -7,3 +7,4 @@
#include "cond_fmax-3.c"
/* { dg-final { scan-assembler-times
{vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c
index 223c8a6938b..a01eb6af0f5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c
@@ -7,3 +7,4 @@
#include "cond_fmax-4.c"
/* { dg-final { scan-assembler-times
{vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c
index 2a28941eee2..77ba2e00bf3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c
@@ -27,3 +27,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times
{vfnmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 { xfail riscv*-*-* } } } */
/* { dg-final { scan-assembler-times
{vfmsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c
index d1826f3fde1..2fa1a2a8308 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c
@@ -27,3 +27,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times
{vfnmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 { xfail riscv*-*-* } } } */
/* { dg-final { scan-assembler-times
{vfmsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c
index 57458239b80..a30362dbb57 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c
@@ -27,3 +27,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times
{vfnmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 { xfail riscv*-*-* } } } */
/* { dg-final { scan-assembler-times
{vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c
index b5ed7045ae2..3389c443325 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c
@@ -27,3 +27,5 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times
{vfnmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 { xfail riscv*-*-* } } } */
/* { dg-final { scan-assembler-times
{vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* NOTE: 3 vmerge is need for other purpose. */
+/* { dg-final { scan-assembler-times {\tvmerge\.vvm\t} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c
index b5ed7045ae2..3389c443325 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c
@@ -27,3 +27,5 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times
{vfnmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 { xfail riscv*-*-* } } } */
/* { dg-final { scan-assembler-times
{vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* NOTE: 3 vmerge is need for other purpose. */
+/* { dg-final { scan-assembler-times {\tvmerge\.vvm\t} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c
index c5c8af86a81..6c3fdb96883 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c
@@ -27,3 +27,5 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times
{vfnmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 { xfail riscv*-*-* } } } */
/* { dg-final { scan-assembler-times
{vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* NOTE: 3 vmerge is need for other purpose. */
+/* { dg-final { scan-assembler-times {\tvmerge\.vvm\t} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c
index 94cec7ff0b1..d8a2e88abe0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c
@@ -27,3 +27,4 @@
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times
{vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c
index c8ada38c002..a64258140e6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c
@@ -26,3 +26,4 @@
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times
{vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c
index bd325ea84ee..0dcd0d44bdc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c
@@ -27,3 +27,4 @@
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times
{vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c
index 118c9a40e8f..af688418e9a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c
@@ -27,3 +27,4 @@
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times
{vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c
new file mode 100644
index 00000000000..c8c3f4fe418
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d
--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include <stdint-gcc.h>
+
+#define DEF_LOOP(TYPE, PRED_TYPE, NAME, CONST)
\
+ void __attribute__ ((noipa))
\
+ test_##TYPE##_##NAME (TYPE *__restrict x, TYPE *__restrict y,
\
+ PRED_TYPE *__restrict pred, TYPE *__restrict merged, \
+ int n) \
+ {
\
+ for (int i = 0; i < n; ++i)
\
+ x[i] = pred[i] != 1 ? y[i] * (TYPE) CONST : merged[i];
\
+ }
+
+#define TEST_TYPE(T, TYPE, PRED_TYPE)
\
+ T (TYPE, PRED_TYPE, half, 0.5)
\
+ T (TYPE, PRED_TYPE, two, 2.0)
\
+ T (TYPE, PRED_TYPE, four, 4.0)
+
+#define TEST_ALL(T)
\
+ TEST_TYPE (T, _Float16, int16_t)
\
+ TEST_TYPE (T, float, int32_t)
\
+ TEST_TYPE (T, double, int64_t)
+
+TEST_ALL (DEF_LOOP)
+
+/* { dg-final { scan-assembler-times
{vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c
new file mode 100644
index 00000000000..656e70eaff8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c
@@ -0,0 +1,33 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable
-fno-vect-cost-model" } */
+
+#include "cond_fmul-5.c"
+
+#define N 99
+
+#define TEST_LOOP(TYPE, PRED_TYPE, NAME, CONST)
\
+ {
\
+ TYPE x[N], y[N], merged[N];
\
+ PRED_TYPE pred[N];
\
+ for (int i = 0; i < N; ++i)
\
+ {
\
+ y[i] = i * i; \
+ pred[i] = i % 3; \
+ merged[i] = i; \
+ }
\
+ test_##TYPE##_##NAME (x, y, pred, merged, N);
\
+ for (int i = 0; i < N; ++i)
\
+ {
\
+ TYPE expected = i % 3 != 1 ? y[i] * (TYPE) CONST : merged[i]; \
+ if (x[i] != expected) \
+ __builtin_abort (); \
+ asm volatile ("" ::: "memory"); \
+ }
\
+ }
+
+int
+main (void)
+{
+ TEST_ALL (TEST_LOOP)
+ return 0;
+}
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c
index 70347861011..85f71c5cf5d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c
@@ -47,3 +47,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t}
4 } } */
/* { dg-final { scan-assembler-times
{vminu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
/* { dg-final { scan-assembler-times
{vmaxu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c
index 44cbbe61845..edb87211540 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c
@@ -47,3 +47,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t}
4 } } */
/* { dg-final { scan-assembler-times
{vminu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
/* { dg-final { scan-assembler-times
{vmaxu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c
index 220a37690dc..a8742a96f53 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c
@@ -47,3 +47,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t}
4 } } */
/* { dg-final { scan-assembler-times
{vminu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
/* { dg-final { scan-assembler-times
{vmaxu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c
index 0763d928789..cf348bfeaa4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c
@@ -47,3 +47,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t}
4 } } */
/* { dg-final { scan-assembler-times
{vminu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
/* { dg-final { scan-assembler-times
{vmaxu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c
index 304c9eeb051..e21162e5af3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c
@@ -47,3 +47,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t}
4 } } */
/* { dg-final { scan-assembler-times
{vminu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
/* { dg-final { scan-assembler-times
{vmaxu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c
index 6bf25383dee..eed38f1d4aa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c
@@ -31,3 +31,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vsll\.vi\s+v[0-9]+,v[0-9]+,3,v0.t} 8 } }
*/
/* { dg-final { scan-assembler-times {vsra\.vi\s+v[0-9]+,v[0-9]+,3,v0.t} 4 } }
*/
/* { dg-final { scan-assembler-times {vsrl\.vi\s+v[0-9]+,v[0-9]+,3,v0.t} 4 } }
*/
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c
index 2edf38f89bd..da888dae13e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c
@@ -31,3 +31,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vsll\.vi\s+v[0-9]+,v[0-9]+,3,v0.t} 8 } }
*/
/* { dg-final { scan-assembler-times {vsra\.vi\s+v[0-9]+,v[0-9]+,3,v0.t} 4 } }
*/
/* { dg-final { scan-assembler-times {vsrl\.vi\s+v[0-9]+,v[0-9]+,3,v0.t} 4 } }
*/
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c
index 84f91ee2668..d20a2c2175e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c
@@ -31,3 +31,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vsll\.vi\s+v[0-9]+,v[0-9]+,3,v0.t} 8 } }
*/
/* { dg-final { scan-assembler-times {vsra\.vi\s+v[0-9]+,v[0-9]+,3,v0.t} 4 } }
*/
/* { dg-final { scan-assembler-times {vsrl\.vi\s+v[0-9]+,v[0-9]+,3,v0.t} 4 } }
*/
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c
index a4be0b35aaf..369f996efcb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c
@@ -31,3 +31,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vsll\.vi\s+v[0-9]+,v[0-9]+,3,v0.t} 8 } }
*/
/* { dg-final { scan-assembler-times {vsra\.vi\s+v[0-9]+,v[0-9]+,3,v0.t} 4 } }
*/
/* { dg-final { scan-assembler-times {vsrl\.vi\s+v[0-9]+,v[0-9]+,3,v0.t} 4 } }
*/
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c
index 06a0a1aaecd..0bb06935d62 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c
@@ -27,3 +27,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vsll\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t}
4 } } */
/* { dg-final { scan-assembler-times {vsra\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t}
2 } } */
/* { dg-final { scan-assembler-times {vsrl\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t}
2 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c
index 3b1c4859e05..2913d236151 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c
@@ -25,3 +25,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vsll\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t}
2 } } */
/* { dg-final { scan-assembler-times {vsra\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t}
1 } } */
/* { dg-final { scan-assembler-times {vsrl\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t}
1 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c
index d44cf43eeb0..df337974216 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c
@@ -27,3 +27,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vsll\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t}
4 } } */
/* { dg-final { scan-assembler-times {vsra\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t}
2 } } */
/* { dg-final { scan-assembler-times {vsrl\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t}
2 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c
index e68289be5e0..bf7f941a4dc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c
@@ -27,3 +27,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vsll\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t}
4 } } */
/* { dg-final { scan-assembler-times {vsra\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t}
2 } } */
/* { dg-final { scan-assembler-times {vsrl\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t}
2 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c
index 892bc08407d..160ead194a5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c
@@ -27,3 +27,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vsll\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t}
4 } } */
/* { dg-final { scan-assembler-times {vsra\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t}
2 } } */
/* { dg-final { scan-assembler-times {vsrl\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t}
2 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
index 21219b43d9d..6eece89bfa5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
@@ -22,3 +22,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {\tvfsqrt\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 }
} */
/* { dg-final { scan-assembler
{\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
index 2fcdc339e70..d6cd5ac734f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
@@ -22,3 +22,4 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {\tvfsqrt\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 }
} */
/* { dg-final { scan-assembler
{\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c
index 8076243f7d4..24e01a92d64 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c
@@ -41,3 +41,5 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } }
*/
/* { dg-final { scan-assembler-times {\tvfabs\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } }
*/
/* { dg-final { scan-assembler-times {\tvfneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } }
*/
+/* NOTE: int abs operator cannot combine the vmerge. */
+/* { dg-final { scan-assembler-times {\tvmerge\.vvm\t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c
index 8e44301ae80..3b967bb50e5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c
@@ -44,3 +44,5 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } }
*/
/* { dg-final { scan-assembler-times {\tvfabs\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } }
*/
/* { dg-final { scan-assembler-times {\tvfneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } }
*/
+/* NOTE: int abs operator cannot combine the vmerge. */
+/* { dg-final { scan-assembler-times {\tvmerge\.vvm\t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c
index 6da5b6e42e3..e458a753c8e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c
@@ -41,3 +41,5 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } }
*/
/* { dg-final { scan-assembler-times {\tvfabs\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } }
*/
/* { dg-final { scan-assembler-times {\tvfneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } }
*/
+/* NOTE: int abs operator cannot combine the vmerge. */
+/* { dg-final { scan-assembler-times {\tvmerge\.vvm\t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c
index 5428c289d22..76a517d4b37 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c
@@ -41,3 +41,5 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } }
*/
/* { dg-final { scan-assembler-times {\tvfabs\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } }
*/
/* { dg-final { scan-assembler-times {\tvfneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } }
*/
+/* NOTE: int abs operator cannot combine the vmerge. */
+/* { dg-final { scan-assembler-times {\tvmerge\.vvm\t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c
index 8e567378d0d..784e522550b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c
@@ -34,3 +34,5 @@ TEST_ALL (DEF_LOOP)
/* NOTE: int abs operator is converted to vmslt + vneg.v */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 12 } }
*/
/* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } }
*/
+/* NOTE: int abs operator cannot combine the vmerge. */
+/* { dg-final { scan-assembler-times {\tvmerge\.vvm\t} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c
index 65a36d0e52a..6a488e95e86 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c
@@ -37,3 +37,5 @@ TEST_ALL (DEF_LOOP)
/* NOTE: int abs operator is converted to vmslt + vneg.v */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 12 } }
*/
/* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } }
*/
+/* NOTE: int abs operator cannot combine the vmerge. */
+/* { dg-final { scan-assembler-times {\tvmerge\.vvm\t} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c
index 356fe9fc25a..d8addfc7dd0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c
@@ -34,3 +34,5 @@ TEST_ALL (DEF_LOOP)
/* NOTE: int abs operator is converted to vmslt + vneg.v */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 12 } }
*/
/* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } }
*/
+/* NOTE: int abs operator cannot combine the vmerge. */
+/* { dg-final { scan-assembler-times {\tvmerge\.vvm\t} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c
index 5208a858882..c6bf77dfa24 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c
@@ -34,3 +34,5 @@ TEST_ALL (DEF_LOOP)
/* NOTE: int abs operator is converted to vmslt + vneg.v */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 12 } }
*/
/* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } }
*/
+/* NOTE: int abs operator cannot combine the vmerge. */
+/* { dg-final { scan-assembler-times {\tvmerge\.vvm\t} 6 } } */
--
2.36.3
