From: Pan Li <pan2...@intel.com>
This patch would like to allow the VLS mode autovec for the
floating-point binary operation MAX/MIN.
Given below code example:
test (float *out, float *in1, float *in2)
{
for (int i = 0; i < 128; i++)
out[i] = in1[i] > in2[i] ? in1[i] : in2[i];
// Or out[i] = fmax (in1[i], in2[i]);
}
Before this patch:
test:
csrr a4,vlenb
slli a4,a4,1
li a5,128
bleu a5,a4,.L2
mv a5,a4
.L2:
vsetvli zero,a5,e32,m8,ta,ma
vle32.v v16,0(a1)
vle32.v v8,0(a2)
vsetvli a3,zero,e32,m8,ta,ma
vmfgt.vv v0,v16,v8
vmerge.vvm v8,v8,v16,v0
vsetvli zero,a5,e32,m8,ta,ma
vse32.v v8,0(a0)
ret
After this patch:
test:
li a5,128
vsetvli zero,a5,e32,m1,ta,ma
vle32.v v1,0(a1)
vle32.v v2,0(a2)
vfmax.vv v1,v1,v2
vse32.v v1,0(a0)
ret
This MAX/MIN autovec acts on function call like fmaxf/fmax in math.h
too. And it depends on the option -ffast-math.
Signed-off-by: Pan Li <pan2...@intel.com>
gcc/ChangeLog:
* config/riscv/autovec-vls.md (<optab><mode>3): New pattern for
fmax/fmin
* config/riscv/vector.md: Add VLS modes to vfmax/vfmin.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/def.h: New macros.
* gcc.target/riscv/rvv/autovec/vls/floating-point-max-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-max-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-max-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-max-4.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-max-5.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-min-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-min-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-min-5.c: New test.
---
gcc/config/riscv/autovec-vls.md | 23 ++++++++++
gcc/config/riscv/vector.md | 12 +++---
.../gcc.target/riscv/rvv/autovec/vls/def.h | 16 +++++++
.../rvv/autovec/vls/floating-point-max-1.c | 43 +++++++++++++++++++
.../rvv/autovec/vls/floating-point-max-2.c | 43 +++++++++++++++++++
.../rvv/autovec/vls/floating-point-max-3.c | 43 +++++++++++++++++++
.../rvv/autovec/vls/floating-point-max-4.c | 43 +++++++++++++++++++
.../rvv/autovec/vls/floating-point-max-5.c | 31 +++++++++++++
.../rvv/autovec/vls/floating-point-min-1.c | 43 +++++++++++++++++++
.../rvv/autovec/vls/floating-point-min-2.c | 43 +++++++++++++++++++
.../rvv/autovec/vls/floating-point-min-3.c | 43 +++++++++++++++++++
.../rvv/autovec/vls/floating-point-min-4.c | 43 +++++++++++++++++++
.../rvv/autovec/vls/floating-point-min-5.c | 31 +++++++++++++
13 files changed, 451 insertions(+), 6 deletions(-)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-3.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-4.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-5.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-3.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-5.c
diff --git a/gcc/config/riscv/autovec-vls.md b/gcc/config/riscv/autovec-vls.md
index 4ca640c11e2..7ef29637e33 100644
--- a/gcc/config/riscv/autovec-vls.md
+++ b/gcc/config/riscv/autovec-vls.md
@@ -232,6 +232,29 @@ (define_insn_and_split "<optab><mode>3"
[(set_attr "type" "vector")]
)
+;; -------------------------------------------------------------------------
+;; Includes:
+;; - vfmin.vv/vfmax.vv
+;; - vfmin.vf/vfmax.vf
+;; - fmax/fmaxf in math.h
+;; -------------------------------------------------------------------------
+(define_insn_and_split "<optab><mode>3"
+ [(set (match_operand:VLSF 0 "register_operand")
+ (any_float_binop_nofrm:VLSF
+ (match_operand:VLSF 1 "<binop_rhs1_predicate>")
+ (match_operand:VLSF 2 "<binop_rhs2_predicate>")))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+{
+ riscv_vector::emit_vlmax_insn (code_for_pred (<CODE>, <MODE>mode),
+ riscv_vector::BINARY_OP, operands);
+ DONE;
+}
+[(set_attr "type" "vector")]
+)
+
;;
-------------------------------------------------------------------------------
;; ---- [INT] Unary operations
;;
-------------------------------------------------------------------------------
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 6fe750ca8a4..9d7b4bbe1d4 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -6050,8 +6050,8 @@ (define_insn "@pred_<optab><mode>"
(symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<optab><mode>"
- [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
- (if_then_else:VF
+ [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
+ (if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
(match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
@@ -6060,10 +6060,10 @@ (define_insn "@pred_<optab><mode>"
(match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (any_float_binop_nofrm:VF
- (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
- (match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
- (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
+ (any_float_binop_nofrm:V_VLSF
+ (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
+ (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr"))
+ (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu,
0")))]
"TARGET_VECTOR"
"vf<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
index 476f966c427..2e07e908736 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
@@ -143,6 +143,14 @@ typedef double v512df __attribute__ ((vector_size (4096)));
a[i] = b[i] OP c[i] ? b[i] : c[i];
\
}
+#define DEF_MINMAX_VX(PREFIX, NUM, TYPE, OP)
\
+ void __attribute__ ((noinline, noclone))
\
+ PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b, TYPE c)
\
+ {
\
+ for (int i = 0; i < NUM; ++i)
\
+ a[i] = b[i] OP c ? b[i] : c;
\
+ }
+
#define DEF_OP_VI_7(PREFIX, NUM, TYPE, OP)
\
void __attribute__ ((noinline, noclone))
\
PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b, TYPE *restrict c)
\
@@ -159,6 +167,14 @@ typedef double v512df __attribute__ ((vector_size (4096)));
a[i] = OP b[i];
\
}
+#define DEF_CALL_VV(PREFIX, NUM, TYPE, CALL)
\
+ void __attribute__ ((noinline, noclone))
\
+ PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b, TYPE *restrict c)
\
+ {
\
+ for (int i = 0; i < NUM; ++i)
\
+ a[i] = CALL (b[i], c[i]);
\
+ }
+
#define DEF_CONST(TYPE, VAL, NUM)
\
void const_##TYPE##_##NUM (TYPE *restrict a)
\
{
\
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-1.c
new file mode 100644
index 00000000000..8d3cd2aa538
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-1.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3
-fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8
-ffast-math" } */
+
+#include "def.h"
+
+DEF_MINMAX_VV (max, 1, _Float16, >)
+DEF_MINMAX_VV (max, 2, _Float16, >)
+DEF_MINMAX_VV (max, 4, _Float16, >)
+DEF_MINMAX_VV (max, 8, _Float16, >)
+DEF_MINMAX_VV (max, 16, _Float16, >)
+DEF_MINMAX_VV (max, 32, _Float16, >)
+DEF_MINMAX_VV (max, 64, _Float16, >)
+DEF_MINMAX_VV (max, 128, _Float16, >)
+DEF_MINMAX_VV (max, 256, _Float16, >)
+DEF_MINMAX_VV (max, 512, _Float16, >)
+DEF_MINMAX_VV (max, 1024, _Float16, >)
+DEF_MINMAX_VV (max, 2048, _Float16, >)
+
+DEF_MINMAX_VV (max, 1, float, >)
+DEF_MINMAX_VV (max, 2, float, >)
+DEF_MINMAX_VV (max, 4, float, >)
+DEF_MINMAX_VV (max, 8, float, >)
+DEF_MINMAX_VV (max, 16, float, >)
+DEF_MINMAX_VV (max, 32, float, >)
+DEF_MINMAX_VV (max, 64, float, >)
+DEF_MINMAX_VV (max, 128, float, >)
+DEF_MINMAX_VV (max, 256, float, >)
+DEF_MINMAX_VV (max, 512, float, >)
+DEF_MINMAX_VV (max, 1024, float, >)
+
+DEF_MINMAX_VV (max, 1, double, >)
+DEF_MINMAX_VV (max, 2, double, >)
+DEF_MINMAX_VV (max, 4, double, >)
+DEF_MINMAX_VV (max, 8, double, >)
+DEF_MINMAX_VV (max, 16, double, >)
+DEF_MINMAX_VV (max, 32, double, >)
+DEF_MINMAX_VV (max, 64, double, >)
+DEF_MINMAX_VV (max, 128, double, >)
+DEF_MINMAX_VV (max, 256, double, >)
+DEF_MINMAX_VV (max, 512, double, >)
+
+/* { dg-final { scan-assembler-times
{vfmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-2.c
new file mode 100644
index 00000000000..a13de042041
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-2.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3
-fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8
-ffast-math" } */
+
+#include "def.h"
+
+DEF_MINMAX_VX (max, 1, _Float16, >)
+DEF_MINMAX_VX (max, 2, _Float16, >)
+DEF_MINMAX_VX (max, 4, _Float16, >)
+DEF_MINMAX_VX (max, 8, _Float16, >)
+DEF_MINMAX_VX (max, 16, _Float16, >)
+DEF_MINMAX_VX (max, 32, _Float16, >)
+DEF_MINMAX_VX (max, 64, _Float16, >)
+DEF_MINMAX_VX (max, 128, _Float16, >)
+DEF_MINMAX_VX (max, 256, _Float16, >)
+DEF_MINMAX_VX (max, 512, _Float16, >)
+DEF_MINMAX_VX (max, 1024, _Float16, >)
+DEF_MINMAX_VX (max, 2048, _Float16, >)
+
+DEF_MINMAX_VX (max, 1, float, >)
+DEF_MINMAX_VX (max, 2, float, >)
+DEF_MINMAX_VX (max, 4, float, >)
+DEF_MINMAX_VX (max, 8, float, >)
+DEF_MINMAX_VX (max, 16, float, >)
+DEF_MINMAX_VX (max, 32, float, >)
+DEF_MINMAX_VX (max, 64, float, >)
+DEF_MINMAX_VX (max, 128, float, >)
+DEF_MINMAX_VX (max, 256, float, >)
+DEF_MINMAX_VX (max, 512, float, >)
+DEF_MINMAX_VX (max, 1024, float, >)
+
+DEF_MINMAX_VX (max, 1, double, >)
+DEF_MINMAX_VX (max, 2, double, >)
+DEF_MINMAX_VX (max, 4, double, >)
+DEF_MINMAX_VX (max, 8, double, >)
+DEF_MINMAX_VX (max, 16, double, >)
+DEF_MINMAX_VX (max, 32, double, >)
+DEF_MINMAX_VX (max, 64, double, >)
+DEF_MINMAX_VX (max, 128, double, >)
+DEF_MINMAX_VX (max, 256, double, >)
+DEF_MINMAX_VX (max, 512, double, >)
+
+/* { dg-final { scan-assembler-times
{vfmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-3.c
new file mode 100644
index 00000000000..108a883bba5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-3.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3
-fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8
-ffast-math" } */
+
+#include "def.h"
+
+DEF_MINMAX_VV (max, 1, _Float16, >=)
+DEF_MINMAX_VV (max, 2, _Float16, >=)
+DEF_MINMAX_VV (max, 4, _Float16, >=)
+DEF_MINMAX_VV (max, 8, _Float16, >=)
+DEF_MINMAX_VV (max, 16, _Float16, >=)
+DEF_MINMAX_VV (max, 32, _Float16, >=)
+DEF_MINMAX_VV (max, 64, _Float16, >=)
+DEF_MINMAX_VV (max, 128, _Float16, >=)
+DEF_MINMAX_VV (max, 256, _Float16, >=)
+DEF_MINMAX_VV (max, 512, _Float16, >=)
+DEF_MINMAX_VV (max, 1024, _Float16, >=)
+DEF_MINMAX_VV (max, 2048, _Float16, >=)
+
+DEF_MINMAX_VV (max, 1, float, >=)
+DEF_MINMAX_VV (max, 2, float, >=)
+DEF_MINMAX_VV (max, 4, float, >=)
+DEF_MINMAX_VV (max, 8, float, >=)
+DEF_MINMAX_VV (max, 16, float, >=)
+DEF_MINMAX_VV (max, 32, float, >=)
+DEF_MINMAX_VV (max, 64, float, >=)
+DEF_MINMAX_VV (max, 128, float, >=)
+DEF_MINMAX_VV (max, 256, float, >=)
+DEF_MINMAX_VV (max, 512, float, >=)
+DEF_MINMAX_VV (max, 1024, float, >=)
+
+DEF_MINMAX_VV (max, 1, double, >=)
+DEF_MINMAX_VV (max, 2, double, >=)
+DEF_MINMAX_VV (max, 4, double, >=)
+DEF_MINMAX_VV (max, 8, double, >=)
+DEF_MINMAX_VV (max, 16, double, >=)
+DEF_MINMAX_VV (max, 32, double, >=)
+DEF_MINMAX_VV (max, 64, double, >=)
+DEF_MINMAX_VV (max, 128, double, >=)
+DEF_MINMAX_VV (max, 256, double, >=)
+DEF_MINMAX_VV (max, 512, double, >=)
+
+/* { dg-final { scan-assembler-times
{vfmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-4.c
new file mode 100644
index 00000000000..d74801887b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-4.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3
-fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8
-ffast-math" } */
+
+#include "def.h"
+
+DEF_MINMAX_VX (max, 1, _Float16, >=)
+DEF_MINMAX_VX (max, 2, _Float16, >=)
+DEF_MINMAX_VX (max, 4, _Float16, >=)
+DEF_MINMAX_VX (max, 8, _Float16, >=)
+DEF_MINMAX_VX (max, 16, _Float16, >=)
+DEF_MINMAX_VX (max, 32, _Float16, >=)
+DEF_MINMAX_VX (max, 64, _Float16, >=)
+DEF_MINMAX_VX (max, 128, _Float16, >=)
+DEF_MINMAX_VX (max, 256, _Float16, >=)
+DEF_MINMAX_VX (max, 512, _Float16, >=)
+DEF_MINMAX_VX (max, 1024, _Float16, >=)
+DEF_MINMAX_VX (max, 2048, _Float16, >=)
+
+DEF_MINMAX_VX (max, 1, float, >=)
+DEF_MINMAX_VX (max, 2, float, >=)
+DEF_MINMAX_VX (max, 4, float, >=)
+DEF_MINMAX_VX (max, 8, float, >=)
+DEF_MINMAX_VX (max, 16, float, >=)
+DEF_MINMAX_VX (max, 32, float, >=)
+DEF_MINMAX_VX (max, 64, float, >=)
+DEF_MINMAX_VX (max, 128, float, >=)
+DEF_MINMAX_VX (max, 256, float, >=)
+DEF_MINMAX_VX (max, 512, float, >=)
+DEF_MINMAX_VX (max, 1024, float, >=)
+
+DEF_MINMAX_VX (max, 1, double, >=)
+DEF_MINMAX_VX (max, 2, double, >=)
+DEF_MINMAX_VX (max, 4, double, >=)
+DEF_MINMAX_VX (max, 8, double, >=)
+DEF_MINMAX_VX (max, 16, double, >=)
+DEF_MINMAX_VX (max, 32, double, >=)
+DEF_MINMAX_VX (max, 64, double, >=)
+DEF_MINMAX_VX (max, 128, double, >=)
+DEF_MINMAX_VX (max, 256, double, >=)
+DEF_MINMAX_VX (max, 512, double, >=)
+
+/* { dg-final { scan-assembler-times
{vfmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-5.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-5.c
new file mode 100644
index 00000000000..775ddb1d25e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-5.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3
-fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8
-ffast-math" } */
+
+#include "def.h"
+#include "math.h"
+
+DEF_CALL_VV (max, 1, float, fmaxf)
+DEF_CALL_VV (max, 2, float, fmaxf)
+DEF_CALL_VV (max, 4, float, fmaxf)
+DEF_CALL_VV (max, 8, float, fmaxf)
+DEF_CALL_VV (max, 16, float, fmaxf)
+DEF_CALL_VV (max, 32, float, fmaxf)
+DEF_CALL_VV (max, 64, float, fmaxf)
+DEF_CALL_VV (max, 128, float, fmaxf)
+DEF_CALL_VV (max, 256, float, fmaxf)
+DEF_CALL_VV (max, 512, float, fmaxf)
+DEF_CALL_VV (max, 1024, float, fmaxf)
+
+DEF_CALL_VV (max, 1, double, fmax)
+DEF_CALL_VV (max, 2, double, fmax)
+DEF_CALL_VV (max, 4, double, fmax)
+DEF_CALL_VV (max, 8, double, fmax)
+DEF_CALL_VV (max, 16, double, fmax)
+DEF_CALL_VV (max, 32, double, fmax)
+DEF_CALL_VV (max, 64, double, fmax)
+DEF_CALL_VV (max, 128, double, fmax)
+DEF_CALL_VV (max, 256, double, fmax)
+DEF_CALL_VV (max, 512, double, fmax)
+
+/* { dg-final { scan-assembler-times
{vfmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 19 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-1.c
new file mode 100644
index 00000000000..e082c47b044
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-1.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3
-fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8
-ffast-math" } */
+
+#include "def.h"
+
+DEF_MINMAX_VV (min, 1, _Float16, <)
+DEF_MINMAX_VV (min, 2, _Float16, <)
+DEF_MINMAX_VV (min, 4, _Float16, <)
+DEF_MINMAX_VV (min, 8, _Float16, <)
+DEF_MINMAX_VV (min, 16, _Float16, <)
+DEF_MINMAX_VV (min, 32, _Float16, <)
+DEF_MINMAX_VV (min, 64, _Float16, <)
+DEF_MINMAX_VV (min, 128, _Float16, <)
+DEF_MINMAX_VV (min, 256, _Float16, <)
+DEF_MINMAX_VV (min, 512, _Float16, <)
+DEF_MINMAX_VV (min, 1024, _Float16, <)
+DEF_MINMAX_VV (min, 2048, _Float16, <)
+
+DEF_MINMAX_VV (min, 1, float, <)
+DEF_MINMAX_VV (min, 2, float, <)
+DEF_MINMAX_VV (min, 4, float, <)
+DEF_MINMAX_VV (min, 8, float, <)
+DEF_MINMAX_VV (min, 16, float, <)
+DEF_MINMAX_VV (min, 32, float, <)
+DEF_MINMAX_VV (min, 64, float, <)
+DEF_MINMAX_VV (min, 128, float, <)
+DEF_MINMAX_VV (min, 256, float, <)
+DEF_MINMAX_VV (min, 512, float, <)
+DEF_MINMAX_VV (min, 1024, float, <)
+
+DEF_MINMAX_VV (min, 1, double, <)
+DEF_MINMAX_VV (min, 2, double, <)
+DEF_MINMAX_VV (min, 4, double, <)
+DEF_MINMAX_VV (min, 8, double, <)
+DEF_MINMAX_VV (min, 16, double, <)
+DEF_MINMAX_VV (min, 32, double, <)
+DEF_MINMAX_VV (min, 64, double, <)
+DEF_MINMAX_VV (min, 128, double, <)
+DEF_MINMAX_VV (min, 256, double, <)
+DEF_MINMAX_VV (min, 512, double, <)
+
+/* { dg-final { scan-assembler-times
{vfmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c
new file mode 100644
index 00000000000..1b900522750
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3
-fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8
-ffast-math" } */
+
+#include "def.h"
+
+DEF_MINMAX_VX (min, 1, _Float16, <)
+DEF_MINMAX_VX (min, 2, _Float16, <)
+DEF_MINMAX_VX (min, 4, _Float16, <)
+DEF_MINMAX_VX (min, 8, _Float16, <)
+DEF_MINMAX_VX (min, 16, _Float16, <)
+DEF_MINMAX_VX (min, 32, _Float16, <)
+DEF_MINMAX_VX (min, 64, _Float16, <)
+DEF_MINMAX_VX (min, 128, _Float16, <)
+DEF_MINMAX_VX (min, 256, _Float16, <)
+DEF_MINMAX_VX (min, 512, _Float16, <)
+DEF_MINMAX_VX (min, 1024, _Float16, <)
+DEF_MINMAX_VX (min, 2048, _Float16, <)
+
+DEF_MINMAX_VX (min, 1, float, <)
+DEF_MINMAX_VX (min, 2, float, <)
+DEF_MINMAX_VX (min, 4, float, <)
+DEF_MINMAX_VX (min, 8, float, <)
+DEF_MINMAX_VX (min, 16, float, <)
+DEF_MINMAX_VX (min, 32, float, <)
+DEF_MINMAX_VX (min, 64, float, <)
+DEF_MINMAX_VX (min, 128, float, <)
+DEF_MINMAX_VX (min, 256, float, <)
+DEF_MINMAX_VX (min, 512, float, <)
+DEF_MINMAX_VX (min, 1024, float, <)
+
+DEF_MINMAX_VX (min, 1, double, <)
+DEF_MINMAX_VX (min, 2, double, <)
+DEF_MINMAX_VX (min, 4, double, <)
+DEF_MINMAX_VX (min, 8, double, <)
+DEF_MINMAX_VX (min, 16, double, <)
+DEF_MINMAX_VX (min, 32, double, <)
+DEF_MINMAX_VX (min, 64, double, <)
+DEF_MINMAX_VX (min, 128, double, <)
+DEF_MINMAX_VX (min, 256, double, <)
+DEF_MINMAX_VX (min, 512, double, <)
+
+/* { dg-final { scan-assembler-times
{vfmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-3.c
new file mode 100644
index 00000000000..ad05800572f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-3.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3
-fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8
-ffast-math" } */
+
+#include "def.h"
+
+DEF_MINMAX_VV (min, 1, _Float16, <=)
+DEF_MINMAX_VV (min, 2, _Float16, <=)
+DEF_MINMAX_VV (min, 4, _Float16, <=)
+DEF_MINMAX_VV (min, 8, _Float16, <=)
+DEF_MINMAX_VV (min, 16, _Float16, <=)
+DEF_MINMAX_VV (min, 32, _Float16, <=)
+DEF_MINMAX_VV (min, 64, _Float16, <=)
+DEF_MINMAX_VV (min, 128, _Float16, <=)
+DEF_MINMAX_VV (min, 256, _Float16, <=)
+DEF_MINMAX_VV (min, 512, _Float16, <=)
+DEF_MINMAX_VV (min, 1024, _Float16, <=)
+DEF_MINMAX_VV (min, 2048, _Float16, <=)
+
+DEF_MINMAX_VV (min, 1, float, <=)
+DEF_MINMAX_VV (min, 2, float, <=)
+DEF_MINMAX_VV (min, 4, float, <=)
+DEF_MINMAX_VV (min, 8, float, <=)
+DEF_MINMAX_VV (min, 16, float, <=)
+DEF_MINMAX_VV (min, 32, float, <=)
+DEF_MINMAX_VV (min, 64, float, <=)
+DEF_MINMAX_VV (min, 128, float, <=)
+DEF_MINMAX_VV (min, 256, float, <=)
+DEF_MINMAX_VV (min, 512, float, <=)
+DEF_MINMAX_VV (min, 1024, float, <=)
+
+DEF_MINMAX_VV (min, 1, double, <=)
+DEF_MINMAX_VV (min, 2, double, <=)
+DEF_MINMAX_VV (min, 4, double, <=)
+DEF_MINMAX_VV (min, 8, double, <=)
+DEF_MINMAX_VV (min, 16, double, <=)
+DEF_MINMAX_VV (min, 32, double, <=)
+DEF_MINMAX_VV (min, 64, double, <=)
+DEF_MINMAX_VV (min, 128, double, <=)
+DEF_MINMAX_VV (min, 256, double, <=)
+DEF_MINMAX_VV (min, 512, double, <=)
+
+/* { dg-final { scan-assembler-times
{vfmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c
new file mode 100644
index 00000000000..5d4109aa3c2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3
-fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8
-ffast-math" } */
+
+#include "def.h"
+
+DEF_MINMAX_VX (min, 1, _Float16, <=)
+DEF_MINMAX_VX (min, 2, _Float16, <=)
+DEF_MINMAX_VX (min, 4, _Float16, <=)
+DEF_MINMAX_VX (min, 8, _Float16, <=)
+DEF_MINMAX_VX (min, 16, _Float16, <=)
+DEF_MINMAX_VX (min, 32, _Float16, <=)
+DEF_MINMAX_VX (min, 64, _Float16, <=)
+DEF_MINMAX_VX (min, 128, _Float16, <=)
+DEF_MINMAX_VX (min, 256, _Float16, <=)
+DEF_MINMAX_VX (min, 512, _Float16, <=)
+DEF_MINMAX_VX (min, 1024, _Float16, <=)
+DEF_MINMAX_VX (min, 2048, _Float16, <=)
+
+DEF_MINMAX_VX (min, 1, float, <=)
+DEF_MINMAX_VX (min, 2, float, <=)
+DEF_MINMAX_VX (min, 4, float, <=)
+DEF_MINMAX_VX (min, 8, float, <=)
+DEF_MINMAX_VX (min, 16, float, <=)
+DEF_MINMAX_VX (min, 32, float, <=)
+DEF_MINMAX_VX (min, 64, float, <=)
+DEF_MINMAX_VX (min, 128, float, <=)
+DEF_MINMAX_VX (min, 256, float, <=)
+DEF_MINMAX_VX (min, 512, float, <=)
+DEF_MINMAX_VX (min, 1024, float, <=)
+
+DEF_MINMAX_VX (min, 1, double, <=)
+DEF_MINMAX_VX (min, 2, double, <=)
+DEF_MINMAX_VX (min, 4, double, <=)
+DEF_MINMAX_VX (min, 8, double, <=)
+DEF_MINMAX_VX (min, 16, double, <=)
+DEF_MINMAX_VX (min, 32, double, <=)
+DEF_MINMAX_VX (min, 64, double, <=)
+DEF_MINMAX_VX (min, 128, double, <=)
+DEF_MINMAX_VX (min, 256, double, <=)
+DEF_MINMAX_VX (min, 512, double, <=)
+
+/* { dg-final { scan-assembler-times
{vfmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-5.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-5.c
new file mode 100644
index 00000000000..1e9ff7d5054
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-5.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3
-fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8
-ffast-math" } */
+
+#include "def.h"
+#include "math.h"
+
+DEF_CALL_VV (min, 1, float, fminf)
+DEF_CALL_VV (min, 2, float, fminf)
+DEF_CALL_VV (min, 4, float, fminf)
+DEF_CALL_VV (min, 8, float, fminf)
+DEF_CALL_VV (min, 16, float, fminf)
+DEF_CALL_VV (min, 32, float, fminf)
+DEF_CALL_VV (min, 64, float, fminf)
+DEF_CALL_VV (min, 128, float, fminf)
+DEF_CALL_VV (min, 256, float, fminf)
+DEF_CALL_VV (min, 512, float, fminf)
+DEF_CALL_VV (min, 1024, float, fminf)
+
+DEF_CALL_VV (min, 1, double, fmin)
+DEF_CALL_VV (min, 2, double, fmin)
+DEF_CALL_VV (min, 4, double, fmin)
+DEF_CALL_VV (min, 8, double, fmin)
+DEF_CALL_VV (min, 16, double, fmin)
+DEF_CALL_VV (min, 32, double, fmin)
+DEF_CALL_VV (min, 64, double, fmin)
+DEF_CALL_VV (min, 128, double, fmin)
+DEF_CALL_VV (min, 256, double, fmin)
+DEF_CALL_VV (min, 512, double, fmin)
+
+/* { dg-final { scan-assembler-times
{vfmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 19 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
--
2.34.1
