Hello!
Introduce handling of TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL and
TARGET_SSE_TYPELESS_STORES flags to movoi, movti and movtf move
patterns. Also introduce ssePSmode attribute to determine PSmode at
compile time.
2012-05-10 Uros Bizjak <ubiz...@gmail.com>
* config/i386/i386.md (*movoi_internal_avx): Handle
TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL and TARGET_SSE_TYPELESS_STORES.
(*movti_internal_rex64): Handle TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL.
(*movti_internal_sse): Ditto.
(*movtf_internal): Ditto.
* config/i386/sse.md (ssePSmode): New mode attribute.
(*move<mode>_internal): Use ssePSmode.
(*<sse>_movu<ssemodesuffix><avxsizesuffix>): Ditto.
(*<sse2>_movdqu<avxsizesuffix>): Ditto.
* config/i386/i386.c (standard_sse_constant_opcode): Do not handle
TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL here.
Tested on x86_64-pc-linux-gnu {,-m32}, committed to mainline SVN.
Uros.
Index: config/i386/sse.md
===================================================================
--- config/i386/sse.md (revision 187354)
+++ config/i386/sse.md (working copy)
@@ -337,6 +337,16 @@
(V8SF "V4SF") (V4DF "V2DF")
(V4SF "V2SF")])
+;; Mapping of vector modes ti packed single mode of the same size
+(define_mode_attr ssePSmode
+ [(V32QI "V8SF") (V16QI "V4SF")
+ (V16HI "V8SF") (V8HI "V4SF")
+ (V8SI "V8SF") (V4SI "V4SF")
+ (V4DI "V8SF") (V2DI "V4SF")
+ (V2TI "V8SF") (V1TI "V4SF")
+ (V8SF "V8SF") (V4SF "V4SF")
+ (V4DF "V8SF") (V2DF "V4SF")])
+
;; Mapping of vector modes back to the scalar modes
(define_mode_attr ssescalarmode
[(V32QI "QI") (V16HI "HI") (V8SI "SI") (V4DI "DI")
@@ -420,7 +430,7 @@
})
(define_insn "*mov<mode>_internal"
- [(set (match_operand:V16 0 "nonimmediate_operand" "=x,x ,m")
+ [(set (match_operand:V16 0 "nonimmediate_operand" "=x,x ,m")
(match_operand:V16 1 "nonimmediate_or_sse_const_operand" "C ,xm,x"))]
"TARGET_SSE
&& (register_operand (operands[0], <MODE>mode)
@@ -471,21 +481,18 @@
[(set_attr "type" "sselog1,ssemov,ssemov")
(set_attr "prefix" "maybe_vex")
(set (attr "mode")
- (cond [(and (eq_attr "alternative" "1,2")
- (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL"))
- (if_then_else
- (match_test "GET_MODE_SIZE (<MODE>mode) > 16")
- (const_string "V8SF")
- (const_string "V4SF"))
+ (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
+ (const_string "<ssePSmode>")
+ (and (eq_attr "alternative" "2")
+ (match_test "TARGET_SSE_TYPELESS_STORES"))
+ (const_string "<ssePSmode>")
(match_test "TARGET_AVX")
(const_string "<sseinsnmode>")
- (ior (and (eq_attr "alternative" "1,2")
- (match_test "optimize_function_for_size_p (cfun)"))
- (and (eq_attr "alternative" "2")
- (match_test "TARGET_SSE_TYPELESS_STORES")))
+ (ior (not (match_test "TARGET_SSE2"))
+ (match_test "optimize_function_for_size_p (cfun)"))
(const_string "V4SF")
]
- (const_string "<sseinsnmode>")))])
+ (const_string "<sseinsnmode>")))])
(define_insn "sse2_movq128"
[(set (match_operand:V2DI 0 "register_operand" "=x")
@@ -610,18 +617,16 @@
(set_attr "prefix" "maybe_vex")
(set (attr "mode")
(cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
- (if_then_else
- (match_test "GET_MODE_SIZE (<MODE>mode) > 16")
- (const_string "V8SF")
- (const_string "V4SF"))
+ (const_string "<ssePSmode>")
+ (and (eq_attr "alternative" "1")
+ (match_test "TARGET_SSE_TYPELESS_STORES"))
+ (const_string "<ssePSmode>")
(match_test "TARGET_AVX")
(const_string "<MODE>")
- (ior (match_test "optimize_function_for_size_p (cfun)")
- (and (eq_attr "alternative" "1")
- (match_test "TARGET_SSE_TYPELESS_STORES")))
- (const_string "V4SF")
+ (match_test "optimize_function_for_size_p (cfun)")
+ (const_string "V4SF")
]
- (const_string "<MODE>")))])
+ (const_string "<MODE>")))])
(define_expand "<sse2>_movdqu<avxsizesuffix>"
[(set (match_operand:VI1 0 "nonimmediate_operand")
@@ -658,18 +663,16 @@
(set_attr "prefix" "maybe_vex")
(set (attr "mode")
(cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
- (if_then_else
- (match_test "GET_MODE_SIZE (<MODE>mode) > 16")
- (const_string "V8SF")
- (const_string "V4SF"))
+ (const_string "<ssePSmode>")
+ (and (eq_attr "alternative" "1")
+ (match_test "TARGET_SSE_TYPELESS_STORES"))
+ (const_string "<ssePSmode>")
(match_test "TARGET_AVX")
(const_string "<sseinsnmode>")
- (ior (match_test "optimize_function_for_size_p (cfun)")
- (and (eq_attr "alternative" "1")
- (match_test "TARGET_SSE_TYPELESS_STORES")))
+ (match_test "optimize_function_for_size_p (cfun)")
(const_string "V4SF")
]
- (const_string "<sseinsnmode>")))])
+ (const_string "<sseinsnmode>")))])
(define_insn "<sse3>_lddqu<avxsizesuffix>"
[(set (match_operand:VI1 0 "register_operand" "=x")
Index: config/i386/i386.c
===================================================================
--- config/i386/i386.c (revision 187354)
+++ config/i386/i386.c (working copy)
@@ -8433,20 +8433,16 @@ standard_sse_constant_opcode (rtx insn, rtx x)
switch (get_attr_mode (insn))
{
case MODE_TI:
- if (!TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
- return "%vpxor\t%0, %d0";
+ return "%vpxor\t%0, %d0";
case MODE_V2DF:
- if (!TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
- return "%vxorpd\t%0, %d0";
+ return "%vxorpd\t%0, %d0";
case MODE_V4SF:
return "%vxorps\t%0, %d0";
case MODE_OI:
- if (!TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
- return "vpxor\t%x0, %x0, %x0";
+ return "vpxor\t%x0, %x0, %x0";
case MODE_V4DF:
- if (!TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
- return "vxorpd\t%x0, %x0, %x0";
+ return "vxorpd\t%x0, %x0, %x0";
case MODE_V8SF:
return "vxorps\t%x0, %x0, %x0";
Index: config/i386/i386.md
===================================================================
--- config/i386/i386.md (revision 187354)
+++ config/i386/i386.md (working copy)
@@ -1810,8 +1810,8 @@
(set_attr "length_immediate" "1")])
(define_insn "*movoi_internal_avx"
- [(set (match_operand:OI 0 "nonimmediate_operand" "=x,x,m")
- (match_operand:OI 1 "vector_move_operand" "C,xm,x"))]
+ [(set (match_operand:OI 0 "nonimmediate_operand" "=x,x ,m")
+ (match_operand:OI 1 "vector_move_operand" "C ,xm,x"))]
"TARGET_AVX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
{
switch (which_alternative)
@@ -1822,20 +1822,37 @@
case 2:
if (misaligned_operand (operands[0], OImode)
|| misaligned_operand (operands[1], OImode))
- return "vmovdqu\t{%1, %0|%0, %1}";
+ {
+ if (get_attr_mode (insn) == MODE_V8SF)
+ return "vmovups\t{%1, %0|%0, %1}";
+ else
+ return "vmovdqu\t{%1, %0|%0, %1}";
+ }
else
- return "vmovdqa\t{%1, %0|%0, %1}";
+ {
+ if (get_attr_mode (insn) == MODE_V8SF)
+ return "vmovaps\t{%1, %0|%0, %1}";
+ else
+ return "vmovdqa\t{%1, %0|%0, %1}";
+ }
default:
gcc_unreachable ();
}
}
[(set_attr "type" "sselog1,ssemov,ssemov")
(set_attr "prefix" "vex")
- (set_attr "mode" "OI")])
+ (set (attr "mode")
+ (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
+ (const_string "V8SF")
+ (and (eq_attr "alternative" "2")
+ (match_test "TARGET_SSE_TYPELESS_STORES"))
+ (const_string "V8SF")
+ ]
+ (const_string "OI")))])
(define_insn "*movti_internal_rex64"
- [(set (match_operand:TI 0 "nonimmediate_operand" "=!r,o,x,x,xm")
- (match_operand:TI 1 "general_operand" "riFo,riF,C,xm,x"))]
+ [(set (match_operand:TI 0 "nonimmediate_operand" "=!r ,o ,x,x ,m")
+ (match_operand:TI 1 "general_operand" "riFo,riF,C,xm,x"))]
"TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
{
switch (which_alternative)
@@ -1871,18 +1888,16 @@
[(set_attr "type" "*,*,sselog1,ssemov,ssemov")
(set_attr "prefix" "*,*,maybe_vex,maybe_vex,maybe_vex")
(set (attr "mode")
- (cond [(eq_attr "alternative" "2,3")
- (if_then_else
- (match_test "optimize_function_for_size_p (cfun)")
- (const_string "V4SF")
- (const_string "TI"))
- (eq_attr "alternative" "4")
- (if_then_else
- (ior (match_test "TARGET_SSE_TYPELESS_STORES")
- (match_test "optimize_function_for_size_p (cfun)"))
- (const_string "V4SF")
- (const_string "TI"))]
- (const_string "DI")))])
+ (cond [(eq_attr "alternative" "0,1")
+ (const_string "DI")
+ (ior (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
+ (match_test "optimize_function_for_size_p (cfun)"))
+ (const_string "V4SF")
+ (and (eq_attr "alternative" "4")
+ (match_test "TARGET_SSE_TYPELESS_STORES"))
+ (const_string "V4SF")
+ ]
+ (const_string "TI")))])
(define_split
[(set (match_operand:TI 0 "nonimmediate_operand")
@@ -1893,8 +1908,8 @@
"ix86_split_long_move (operands); DONE;")
(define_insn "*movti_internal_sse"
- [(set (match_operand:TI 0 "nonimmediate_operand" "=x,x,m")
- (match_operand:TI 1 "vector_move_operand" "C,xm,x"))]
+ [(set (match_operand:TI 0 "nonimmediate_operand" "=x,x ,m")
+ (match_operand:TI 1 "vector_move_operand" "C ,xm,x"))]
"TARGET_SSE && !TARGET_64BIT
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
{
@@ -1928,12 +1943,15 @@
[(set_attr "type" "sselog1,ssemov,ssemov")
(set_attr "prefix" "maybe_vex")
(set (attr "mode")
- (cond [(ior (not (match_test "TARGET_SSE2"))
+ (cond [(ior (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
(match_test "optimize_function_for_size_p (cfun)"))
(const_string "V4SF")
(and (eq_attr "alternative" "2")
(match_test "TARGET_SSE_TYPELESS_STORES"))
- (const_string "V4SF")]
+ (const_string "V4SF")
+ (not (match_test "TARGET_SSE2"))
+ (const_string "V4SF")
+ ]
(const_string "TI")))])
(define_insn "*movdi_internal_rex64"
@@ -2813,8 +2831,8 @@
"ix86_expand_move (<MODE>mode, operands); DONE;")
(define_insn "*movtf_internal"
- [(set (match_operand:TF 0 "nonimmediate_operand" "=x,m,x,?*r ,!o")
- (match_operand:TF 1 "general_operand" "xm,x,C,*roF,F*r"))]
+ [(set (match_operand:TF 0 "nonimmediate_operand" "=x,x ,m,?*r ,!o")
+ (match_operand:TF 1 "general_operand" "C ,xm,x,*roF,F*r"))]
"TARGET_SSE2
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))
&& (!can_create_pseudo_p ()
@@ -2829,7 +2847,9 @@
switch (which_alternative)
{
case 0:
+ return standard_sse_constant_opcode (insn, operands[1]);
case 1:
+ case 2:
/* Handle misaligned load/store since we
don't have movmisaligntf pattern. */
if (misaligned_operand (operands[0], TFmode)
@@ -2848,9 +2868,6 @@
return "%vmovdqa\t{%1, %0|%0, %1}";
}
- case 2:
- return standard_sse_constant_opcode (insn, operands[1]);
-
case 3:
case 4:
return "#";
@@ -2859,21 +2876,19 @@
gcc_unreachable ();
}
}
- [(set_attr "type" "ssemov,ssemov,sselog1,*,*")
+ [(set_attr "type" "sselog1,ssemov,ssemov,*,*")
(set_attr "prefix" "maybe_vex,maybe_vex,maybe_vex,*,*")
(set (attr "mode")
- (cond [(eq_attr "alternative" "0,2")
- (if_then_else
- (match_test "optimize_function_for_size_p (cfun)")
- (const_string "V4SF")
- (const_string "TI"))
- (eq_attr "alternative" "1")
- (if_then_else
- (ior (match_test "TARGET_SSE_TYPELESS_STORES")
- (match_test "optimize_function_for_size_p (cfun)"))
- (const_string "V4SF")
- (const_string "TI"))]
- (const_string "DI")))])
+ (cond [(eq_attr "alternative" "3,4")
+ (const_string "DI")
+ (ior (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
+ (match_test "optimize_function_for_size_p (cfun)"))
+ (const_string "V4SF")
+ (and (eq_attr "alternative" "2")
+ (match_test "TARGET_SSE_TYPELESS_STORES"))
+ (const_string "V4SF")
+ ]
+ (const_string "TI")))])
;; Possible store forwarding (partial memory) stall in alternative 4.
(define_insn "*movxf_internal"
