Merge V_128H and V_256H into V_128 and V_256, adjust related patterns.
Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
Ready push to trunk.
gcc/ChangeLog:
* config/i386/sse.md (vec_set<mode>): Removed.
(V_128H): Merge into ..
(V_128): .. this.
(V_256H): Merge into ..
(V_256): .. this.
(V_512): Add V32HF, V32BF.
(*ssse3_palignr<mode>_perm): Adjust mode iterator from V_128H
to V_128.
(vcond<mode><sseintvecmodelower>): Removed
(vcondu<mode><sseintvecmodelower>): Removed.
(avx_vbroadcastf128_<mode>): Refator from V_256H to V_256.
---
gcc/config/i386/sse.md | 65 +++++-------------------------------------
1 file changed, 7 insertions(+), 58 deletions(-)
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index da85223a9b4..b9cf172306c 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -312,17 +312,10 @@ (define_mode_iterator V
;; All 128bit vector modes
(define_mode_iterator V_128
- [V16QI V8HI V4SI V2DI V4SF (V2DF "TARGET_SSE2")])
-
-(define_mode_iterator V_128H
[V16QI V8HI V8HF V8BF V4SI V2DI V4SF (V2DF "TARGET_SSE2")])
;; All 256bit vector modes
(define_mode_iterator V_256
- [V32QI V16HI V8SI V4DI V8SF V4DF])
-
-;; All 256bit vector modes including HF/BF vector modes
-(define_mode_iterator V_256H
[V32QI V16HI V8SI V4DI V8SF V4DF V16HF V16BF])
;; All 128bit and 256bit vector modes
@@ -331,7 +324,7 @@ (define_mode_iterator V_128_256
V16HF V8HF V8SF V4SF V4DF V2DF])
;; All 512bit vector modes
-(define_mode_iterator V_512 [V64QI V32HI V16SI V8DI V16SF V8DF])
+(define_mode_iterator V_512 [V64QI V32HI V16SI V8DI V16SF V8DF V32HF V32BF])
;; All 256bit and 512bit vector modes
(define_mode_iterator V_256_512
@@ -4652,21 +4645,6 @@ (define_expand "vcond<mode><mode>"
DONE;
})
-(define_expand "vcond<mode><sseintvecmodelower>"
- [(set (match_operand:VF_AVX512HFBFVL 0 "register_operand")
- (if_then_else:VF_AVX512HFBFVL
- (match_operator 3 ""
- [(match_operand:<sseintvecmode> 4 "vector_operand")
- (match_operand:<sseintvecmode> 5 "vector_operand")])
- (match_operand:VF_AVX512HFBFVL 1 "general_operand")
- (match_operand:VF_AVX512HFBFVL 2 "general_operand")))]
- "TARGET_AVX512FP16"
-{
- bool ok = ix86_expand_int_vcond (operands);
- gcc_assert (ok);
- DONE;
-})
-
(define_expand "vcond<sseintvecmodelower><mode>"
[(set (match_operand:<sseintvecmode> 0 "register_operand")
(if_then_else:<sseintvecmode>
@@ -11414,20 +11392,6 @@ (define_expand "vec_set<mode>"
DONE;
})
-(define_expand "vec_set<mode>"
- [(match_operand:V8BFH_128 0 "register_operand")
- (match_operand:<ssescalarmode> 1 "register_operand")
- (match_operand 2 "vec_setm_sse41_operand")]
- "TARGET_SSE"
-{
- if (CONST_INT_P (operands[2]))
- ix86_expand_vector_set (false, operands[0], operands[1],
- INTVAL (operands[2]));
- else
- ix86_expand_vector_set_var (operands[0], operands[1], operands[2]);
- DONE;
-})
-
(define_expand "vec_set<mode>"
[(match_operand:V_256_512 0 "register_operand")
(match_operand:<ssescalarmode> 1 "register_operand")
@@ -11884,7 +11848,7 @@ (define_expand "avx512vl_vextractf128<mode>"
(define_expand "avx_vextractf128<mode>"
[(match_operand:<ssehalfvecmode> 0 "nonimmediate_operand")
- (match_operand:V_256H 1 "register_operand")
+ (match_operand:V_256 1 "register_operand")
(match_operand:SI 2 "const_0_to_1_operand")]
"TARGET_AVX"
{
@@ -17326,21 +17290,6 @@ (define_expand "vcondu<VI8F_128:mode>v2di"
DONE;
})
-(define_expand "vcondu<mode><sseintvecmodelower>"
- [(set (match_operand:VF_AVX512FP16VL 0 "register_operand")
- (if_then_else:VF_AVX512FP16VL
- (match_operator 3 ""
- [(match_operand:<sseintvecmode> 4 "vector_operand")
- (match_operand:<sseintvecmode> 5 "vector_operand")])
- (match_operand:VF_AVX512FP16VL 1 "general_operand")
- (match_operand:VF_AVX512FP16VL 2 "general_operand")))]
- "TARGET_AVX512FP16"
-{
- bool ok = ix86_expand_int_vcond (operands);
- gcc_assert (ok);
- DONE;
-})
-
(define_expand "vcondeq<VI8F_128:mode>v2di"
[(set (match_operand:VI8F_128 0 "register_operand")
(if_then_else:VI8F_128
@@ -26879,8 +26828,8 @@ (define_split
"operands[2] = gen_lowpart (<ssehalfvecmode>mode, operands[0]);")
(define_insn "avx_vbroadcastf128_<mode>"
- [(set (match_operand:V_256H 0 "register_operand" "=x,x,x,v,v,v,v")
- (vec_concat:V_256H
+ [(set (match_operand:V_256 0 "register_operand" "=x,x,x,v,v,v,v")
+ (vec_concat:V_256
(match_operand:<ssehalfvecmode> 1 "nonimmediate_operand"
"m,0,?x,m,0,m,0")
(match_dup 1)))]
"TARGET_AVX"
@@ -27206,9 +27155,9 @@ (define_insn "*avx_vperm2f128<mode>_nozero"
(set_attr "mode" "<sseinsnmode>")])
(define_insn "*ssse3_palignr<mode>_perm"
- [(set (match_operand:V_128H 0 "register_operand" "=x,Yw")
- (vec_select:V_128H
- (match_operand:V_128H 1 "register_operand" "0,Yw")
+ [(set (match_operand:V_128 0 "register_operand" "=x,Yw")
+ (vec_select:V_128
+ (match_operand:V_128 1 "register_operand" "0,Yw")
(match_parallel 2 "palignr_operand"
[(match_operand 3 "const_int_operand")])))]
"TARGET_SSSE3"
--
2.31.1
