Many were lacking "prefix" and "prefix_extra", some had a bogus value of
2 for "prefix_extra" (presumably inherited from their SSE5 counterparts,
which are long gone) and a meaningless "prefix_data16" one. Where
missing, "mode" attributes are also added. (Note that "sse4arg" and
"ssemuladd" ones don't need further adjustment in this regard.)
gcc/
* config/i386/sse.md (xop_phadd<u>bw): Add "prefix",
"prefix_extra", and "mode" attributes.
(xop_phadd<u>bd): Likewise.
(xop_phadd<u>bq): Likewise.
(xop_phadd<u>wd): Likewise.
(xop_phadd<u>wq): Likewise.
(xop_phadd<u>dq): Likewise.
(xop_phsubbw): Likewise.
(xop_phsubwd): Likewise.
(xop_phsubdq): Likewise.
(xop_rotl<mode>3): Add "prefix" and "prefix_extra" attributes.
(xop_rotr<mode>3): Likewise.
(xop_frcz<mode>2): Likewise.
(*xop_vmfrcz<mode>2): Likewise.
(xop_vrotl<mode>3): Add "prefix" attribute. Change
"prefix_extra" to 1.
(xop_sha<mode>3): Likewise.
(xop_shl<mode>3): Likewise.
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -24897,7 +24897,10 @@
(const_int 13) (const_int 15)])))))]
"TARGET_XOP"
"vphadd<u>bw\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
+ [(set_attr "type" "sseiadd1")
+ (set_attr "prefix" "vex")
+ (set_attr "prefix_extra" "1")
+ (set_attr "mode" "TI")])
(define_insn "xop_phadd<u>bd"
[(set (match_operand:V4SI 0 "register_operand" "=x")
@@ -24926,7 +24929,10 @@
(const_int 11) (const_int 15)]))))))]
"TARGET_XOP"
"vphadd<u>bd\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
+ [(set_attr "type" "sseiadd1")
+ (set_attr "prefix" "vex")
+ (set_attr "prefix_extra" "1")
+ (set_attr "mode" "TI")])
(define_insn "xop_phadd<u>bq"
[(set (match_operand:V2DI 0 "register_operand" "=x")
@@ -24971,7 +24977,10 @@
(parallel [(const_int 7) (const_int 15)])))))))]
"TARGET_XOP"
"vphadd<u>bq\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
+ [(set_attr "type" "sseiadd1")
+ (set_attr "prefix" "vex")
+ (set_attr "prefix_extra" "1")
+ (set_attr "mode" "TI")])
(define_insn "xop_phadd<u>wd"
[(set (match_operand:V4SI 0 "register_operand" "=x")
@@ -24988,7 +24997,10 @@
(const_int 5) (const_int 7)])))))]
"TARGET_XOP"
"vphadd<u>wd\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
+ [(set_attr "type" "sseiadd1")
+ (set_attr "prefix" "vex")
+ (set_attr "prefix_extra" "1")
+ (set_attr "mode" "TI")])
(define_insn "xop_phadd<u>wq"
[(set (match_operand:V2DI 0 "register_operand" "=x")
@@ -25013,7 +25025,10 @@
(parallel [(const_int 3) (const_int 7)]))))))]
"TARGET_XOP"
"vphadd<u>wq\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
+ [(set_attr "type" "sseiadd1")
+ (set_attr "prefix" "vex")
+ (set_attr "prefix_extra" "1")
+ (set_attr "mode" "TI")])
(define_insn "xop_phadd<u>dq"
[(set (match_operand:V2DI 0 "register_operand" "=x")
@@ -25028,7 +25043,10 @@
(parallel [(const_int 1) (const_int 3)])))))]
"TARGET_XOP"
"vphadd<u>dq\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
+ [(set_attr "type" "sseiadd1")
+ (set_attr "prefix" "vex")
+ (set_attr "prefix_extra" "1")
+ (set_attr "mode" "TI")])
(define_insn "xop_phsubbw"
[(set (match_operand:V8HI 0 "register_operand" "=x")
@@ -25049,7 +25067,10 @@
(const_int 13) (const_int 15)])))))]
"TARGET_XOP"
"vphsubbw\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
+ [(set_attr "type" "sseiadd1")
+ (set_attr "prefix" "vex")
+ (set_attr "prefix_extra" "1")
+ (set_attr "mode" "TI")])
(define_insn "xop_phsubwd"
[(set (match_operand:V4SI 0 "register_operand" "=x")
@@ -25066,7 +25087,10 @@
(const_int 5) (const_int 7)])))))]
"TARGET_XOP"
"vphsubwd\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
+ [(set_attr "type" "sseiadd1")
+ (set_attr "prefix" "vex")
+ (set_attr "prefix_extra" "1")
+ (set_attr "mode" "TI")])
(define_insn "xop_phsubdq"
[(set (match_operand:V2DI 0 "register_operand" "=x")
@@ -25081,7 +25105,10 @@
(parallel [(const_int 1) (const_int 3)])))))]
"TARGET_XOP"
"vphsubdq\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
+ [(set_attr "type" "sseiadd1")
+ (set_attr "prefix" "vex")
+ (set_attr "prefix_extra" "1")
+ (set_attr "mode" "TI")])
;; XOP permute instructions
(define_insn "xop_pperm"
@@ -25209,6 +25236,8 @@
"TARGET_XOP"
"vprot<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseishft")
+ (set_attr "prefix" "vex")
+ (set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
@@ -25224,6 +25253,8 @@
return \"vprot<ssemodesuffix>\t{%3, %1, %0|%0, %1, %3}\";
}
[(set_attr "type" "sseishft")
+ (set_attr "prefix" "vex")
+ (set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
@@ -25264,8 +25295,8 @@
"TARGET_XOP && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"vprot<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseishft")
- (set_attr "prefix_data16" "0")
- (set_attr "prefix_extra" "2")
+ (set_attr "prefix" "vex")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "TI")])
;; XOP packed shift instructions.
@@ -25501,8 +25532,8 @@
"TARGET_XOP && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"vpsha<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseishft")
- (set_attr "prefix_data16" "0")
- (set_attr "prefix_extra" "2")
+ (set_attr "prefix" "vex")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "TI")])
(define_insn "xop_shl<mode>3"
@@ -25520,8 +25551,8 @@
"TARGET_XOP && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"vpshl<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseishft")
- (set_attr "prefix_data16" "0")
- (set_attr "prefix_extra" "2")
+ (set_attr "prefix" "vex")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "TI")])
(define_expand "<insn><mode>3"
@@ -25733,6 +25764,8 @@
"TARGET_XOP"
"vfrcz<ssemodesuffix>\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt1")
+ (set_attr "prefix" "vex")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "<MODE>")])
(define_expand "xop_vmfrcz<mode>2"
@@ -25757,6 +25790,8 @@
"TARGET_XOP"
"vfrcz<ssescalarmodesuffix>\t{%1, %0|%0, %<iptr>1}"
[(set_attr "type" "ssecvt1")
+ (set_attr "prefix" "vex")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "<MODE>")])
(define_insn "xop_maskcmp<mode>3"
