gcc/
* config/xtensa/xtensa.h (XCHAL_HAVE_BE, XCHAL_HAVE_DENSITY,
XCHAL_HAVE_CONST16, XCHAL_HAVE_ABS, XCHAL_HAVE_ADDX,
XCHAL_HAVE_L32R, XSHAL_USE_ABSOLUTE_LITERALS,
XSHAL_HAVE_TEXT_SECTION_LITERALS, XCHAL_HAVE_MAC16,
XCHAL_HAVE_MUL16, XCHAL_HAVE_MUL32, XCHAL_HAVE_MUL32_HIGH,
XCHAL_HAVE_DIV32, XCHAL_HAVE_NSA, XCHAL_HAVE_MINMAX,
XCHAL_HAVE_SEXT, XCHAL_HAVE_LOOPS, XCHAL_HAVE_THREADPTR,
XCHAL_HAVE_RELEASE_SYNC, XCHAL_HAVE_S32C1I,
XCHAL_HAVE_BOOLEANS, XCHAL_HAVE_FP, XCHAL_HAVE_FP_DIV,
XCHAL_HAVE_FP_RECIP, XCHAL_HAVE_FP_SQRT,
XCHAL_HAVE_FP_RSQRT, XCHAL_HAVE_FP_POSTINC, XCHAL_HAVE_DFP,
XCHAL_HAVE_DFP_DIV, XCHAL_HAVE_DFP_RECIP,
XCHAL_HAVE_DFP_SQRT, XCHAL_HAVE_DFP_RSQRT,
XCHAL_HAVE_WINDOWED, XCHAL_NUM_AREGS,
XCHAL_HAVE_WIDE_BRANCHES, XCHAL_HAVE_PREDICTED_BRANCHES,
XCHAL_ICACHE_SIZE, XCHAL_DCACHE_SIZE,
XCHAL_ICACHE_LINESIZE, XCHAL_DCACHE_LINESIZE,
XCHAL_ICACHE_LINEWIDTH, XCHAL_DCACHE_LINEWIDTH,
XCHAL_DCACHE_IS_WRITEBACK, XCHAL_HAVE_MMU,
XCHAL_MMU_MIN_PTE_PAGE_SIZE, XCHAL_HAVE_DEBUG,
XCHAL_NUM_IBREAK, XCHAL_NUM_DBREAK, XCHAL_DEBUGLEVEL,
XCHAL_MAX_INSTRUCTION_SIZE, XCHAL_INST_FETCH_WIDTH,
XSHAL_ABI, XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0,
XCHAL_M_STAGE, XTENSA_MARCH_LATEST, XTENSA_MARCH_EARLIEST,
XCHAL_HAVE_CLAMPS, XCHAL_HAVE_DEPBITS,
XCHAL_HAVE_EXCLUSIVE, XCHAL_HAVE_XEA3): Add builtin-macros
with values from dynconfig.
---
gcc/config/xtensa/xtensa.h | 62 ++++++++++++++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/gcc/config/xtensa/xtensa.h b/gcc/config/xtensa/xtensa.h
index 8ebf37cab33..a65b674915b 100644
--- a/gcc/config/xtensa/xtensa.h
+++ b/gcc/config/xtensa/xtensa.h
@@ -67,6 +67,7 @@ along with GCC; see the file COPYING3. If not see
#endif
+#define XTENSA_CPU_CPP_BUILTIN(OPT) builtin_define_with_int_value (#OPT, OPT)
/* Target CPU builtins. */
#define TARGET_CPU_CPP_BUILTINS() \
do { \
@@ -82,6 +83,67 @@ along with GCC; see the file COPYING3. If not see
builtin_define ("__XTENSA_SOFT_FLOAT__");
\
for (builtin = xtensa_get_config_strings (); *builtin; ++builtin) \
builtin_define (*builtin); \
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_BE);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_DENSITY);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_CONST16);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_ABS);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_ADDX);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_L32R);
\
+ XTENSA_CPU_CPP_BUILTIN(XSHAL_USE_ABSOLUTE_LITERALS); \
+ XTENSA_CPU_CPP_BUILTIN(XSHAL_HAVE_TEXT_SECTION_LITERALS); \
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_MAC16);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_MUL16);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_MUL32);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_MUL32_HIGH);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_DIV32);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_NSA);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_MINMAX);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_SEXT);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_LOOPS);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_THREADPTR);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_RELEASE_SYNC); \
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_S32C1I);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_BOOLEANS);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_FP);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_FP_DIV);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_FP_RECIP);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_FP_SQRT);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_FP_RSQRT);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_FP_POSTINC);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_DFP);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_DFP_DIV);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_DFP_RECIP);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_DFP_SQRT);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_DFP_RSQRT);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_WINDOWED);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_NUM_AREGS);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_WIDE_BRANCHES); \
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_PREDICTED_BRANCHES); \
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_ICACHE_SIZE);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_DCACHE_SIZE);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_ICACHE_LINESIZE);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_DCACHE_LINESIZE);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_ICACHE_LINEWIDTH);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_DCACHE_LINEWIDTH);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_DCACHE_IS_WRITEBACK); \
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_MMU);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_MMU_MIN_PTE_PAGE_SIZE); \
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_DEBUG);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_NUM_IBREAK);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_NUM_DBREAK);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_DEBUGLEVEL);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_MAX_INSTRUCTION_SIZE);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_INST_FETCH_WIDTH);
\
+ XTENSA_CPU_CPP_BUILTIN(XSHAL_ABI);
\
+ XTENSA_CPU_CPP_BUILTIN(XTHAL_ABI_WINDOWED);
\
+ XTENSA_CPU_CPP_BUILTIN(XTHAL_ABI_CALL0);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_M_STAGE);
\
+ XTENSA_CPU_CPP_BUILTIN(XTENSA_MARCH_LATEST);
\
+ XTENSA_CPU_CPP_BUILTIN(XTENSA_MARCH_EARLIEST);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_CLAMPS);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_DEPBITS);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_EXCLUSIVE);
\
+ XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_XEA3);
\
} while (0)
#define CPP_SPEC " %(subtarget_cpp_spec) "
--
2.34.1
