On 4/28/23 00:23, Christoph Muellner wrote:
From: Christoph Müllner <christoph.muell...@vrull.eu>
The XTheadFMemIdx ISA extension provides additional load and store
instructions for floating-point registers with new addressing modes.
The following memory accesses types are supported:
* ftype = [w,d] (single-precision, double-precision)
The following addressing modes are supported:
* register offset with additional immediate offset (4 instructions):
flr<type>, fsr<type>
* zero-extended register offset with additional immediate offset
(4 instructions): flur<type>, fsur<type>
These addressing modes are also part of the similar XTheadMemIdx
ISA extension support, whose code is reused and extended to support
floating-point registers.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_index_reg_class): Also allow
for XTheadFMemIdx.
(riscv_regno_ok_for_index_p): Likewise.
* config/riscv/thead-peephole.md (TARGET_64BIT):
Generalize peepholes for XTheadFMemIdx.
* config/riscv/thead.cc (is_fmemidx_mode): New function.
(th_memidx_classify_address_index): Add support for
XTheadFMemIdx.
(th_fmemidx_output_index): New function.
(th_output_move): Add support for XTheadFMemIdx.
* config/riscv/thead.md (*th_fmemidx_movsf_hardfloat): New INSN.
(*th_fmemidx_movdf_hardfloat_rv64): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xtheadmemidx-helpers.h: Add helpers for
XTheadMemFIdx.
* gcc.target/riscv/xtheadfmemidx-index-update.c: New test.
* gcc.target/riscv/xtheadfmemidx-index-xtheadbb-update.c: New test.
* gcc.target/riscv/xtheadfmemidx-index-xtheadbb.c: New test.
* gcc.target/riscv/xtheadfmemidx-index.c: New test.
* gcc.target/riscv/xtheadfmemidx-uindex-update.c: New test.
* gcc.target/riscv/xtheadfmemidx-uindex-xtheadbb-update.c: New test.
* gcc.target/riscv/xtheadfmemidx-uindex-xtheadbb.c: New test.
* gcc.target/riscv/xtheadfmemidx-uindex.c: New test.
Same core questions/comments as in patch #10 of this series.
jeff
