On Wed, Apr 05, 2023 at 10:17:59AM -0600, Jeff Law wrote:
> > It is true that an instruction like
> > (insn 8 7 9 2 (set (reg:HI 141)
> > (subreg:HI (reg:SI 142) 0)) "aauu.c":6:18 181 {*movhi_internal}
> > (nil))
> > can appear in the IL on WORD_REGISTER_OPERATIONS target, but I think the
> > upper bits shouldn't be random garbage in that case, it should be zero
> > extended or sign extended.
> Well, that's one of the core questions here. What are the state of the
> upper 16 bits of (reg:HI 141)? The WORD_REGISTER_OPERATIONS docs aren't
> 100% clear as we're not really doing any operation.
>
> So again, I think we need to decide if the DSE transformation is correct or
> not. I *think* we can aggree that insn 39 is OK. It's really the semantics
> of insn 47 that I think we need to agree on. What is the state of the upper
> 16 bits of (reg:HI 175) after insn 47?
I'm afraid I don't know the answers here, I think Eric is
WORD_REGISTER_OPERATIONS expert here I think these days (most of the major
targets are !WORD_REGISTER_OPERATIONS).
Intuitively, WORD_REGISTER_OPERATIONS from the description would be
that
(insn 47 35 39 2 (set (reg:HI 175)
(subreg:HI (reg:SI 166) 0)) "pr109040.c":9:11 179 {*movhi_internal}
(expr_list:REG_DEAD (reg:SI 166)
(nil)))
would copy not just the low 16-bits of pseudo 166 to 175, but also the upper
16-bits. But if that is so, then something is broken in the code below.
Some archeology shows that we were doing that on all arches initially
and then
Wed May 13 17:38:35 1998 Richard Kenner <ken...@vlsi1.ultra.nyu.edu>
* combine.c (simplify_comparison, case AND): Don't commute AND
with SUBREG if constant is whole mode and don't do if lowpart
and not WORD_REGISTER_OPERATIONS.
restricted that to WORD_REGISTER_OPERATIONS only.
The whole optimization is then likely
Wed Mar 18 05:54:25 1998 Richard Kenner <ken...@vlsi1.ultra.nyu.edu>
* combine.c (gen_binary): Don't make AND that does nothing.
(simplify_comparison, case AND): Commute AND and SUBREG.
* i386.h (CONST_CONSTS, case CONST_INT): One-byte integers are cost 0.
but the code has been tweaked further many times since then.
> > We substitute that
> > (leu:SI (and:SI (subreg:SI (reg:HI 175) 0)
> > (const_int 2124 [0x84c]))
> > (const_int 5 [0x5]))
> > but then trigger the WORD_REGISTER_OPERATIONS block in simplify_comparison:
> > /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
> > fits in both M1 and M2 and the SUBREG is either paradoxical
> > or represents the low part, permute the SUBREG and the AND
> > and try again. */
> > if (GET_CODE (XEXP (op0, 0)) == SUBREG
> > && CONST_INT_P (XEXP (op0, 1)))
> > {
> > unsigned HOST_WIDE_INT c1 = INTVAL (XEXP (op0, 1));
> > /* Require an integral mode, to avoid creating something like
> > (AND:SF ...). */
> > if ((is_a <scalar_int_mode>
> > (GET_MODE (SUBREG_REG (XEXP (op0, 0))), &tmode))
> > /* It is unsafe to commute the AND into the SUBREG if the
> > SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
> > not defined. As originally written the upper bits
> > have a defined value due to the AND operation.
> > However, if we commute the AND inside the SUBREG then
> > they no longer have defined values and the meaning of
> > the code has been changed.
> > Also C1 should not change value in the smaller mode,
> > see PR67028 (a positive C1 can become negative in the
> > smaller mode, so that the AND does no longer mask the
> > upper bits). */
> > && ((WORD_REGISTER_OPERATIONS
> > && mode_width > GET_MODE_PRECISION (tmode)
> > && mode_width <= BITS_PER_WORD
> > && trunc_int_for_mode (c1, tmode) ==
> > (HOST_WIDE_INT) c1)
> > || (mode_width <= GET_MODE_PRECISION (tmode)
> > && subreg_lowpart_p (XEXP (op0, 0))))
> > && mode_width <= HOST_BITS_PER_WIDE_INT
> > && HWI_COMPUTABLE_MODE_P (tmode)
> > && (c1 & ~mask) == 0
> > && (c1 & ~GET_MODE_MASK (tmode)) == 0
> > && c1 != mask
> > && c1 != GET_MODE_MASK (tmode))
> > {
> > op0 = simplify_gen_binary (AND, tmode,
> > SUBREG_REG (XEXP (op0, 0)),
> > gen_int_mode (c1, tmode));
> > op0 = gen_lowpart (mode, op0);
> > continue;
> > }
> > }
> > c1 is 0x84c. I believe this is the exact spot where things go wrong,
> > and is because for WORD_REGISTER_OPERATIONS we assume something that the
> > DSE added instruction didn't guarantee.
> pan2.li zero'd in on the same block of code.
>
> The leap I'm strugging with is the assertion that this combine code assumes
> something that the DSE added instruction does not guarantee. That's why I
> asked if we agreed that the before/after from DSE was correct or not. I
> think that's still the outstanding question.
Jakub
